公开(公告)号：US09627245B2

公开(公告)日：2017-04-18

申请号：US14197790

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Nicolas Loubet

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/04 ,  H01L29/165

CPC classification number: H01L21/76224 ,  H01L29/045 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

公开(公告)号：US20160035820A1

公开(公告)日：2016-02-04

申请号：US14447678

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  Commissariat a l'Energie Atomique et aux Energies Alternatives ,  GLOBALFOUNDRIES Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

公开(公告)号：US20150255295A1

公开(公告)日：2015-09-10

申请号：US14197790

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Nicolas Loubet

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/045 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

Abstract translation: 本文中公开的一种说明性方法包括形成沟槽以形成具有初始暴露高度和侧壁的初始鳍结构，在至少初始鳍结构的侧壁上形成保护层，从而延伸沟槽的深度，从而 限定一个增加高度的翅片结构，其中绝缘材料层覆盖最终的沟槽并且将保护层置于适当位置，执行翅片氧化热退火工艺以将至少一部分高度翅片结构转换为 隔离材料，去除保护层，以及进行外延沉积工艺以在初始鳍结构的至少部分上形成半导体材料层。

公开(公告)号：US20210003776A1

公开(公告)日：2021-01-07

申请号：US16502667

申请日：2019-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/126

Abstract: One illustrative TE pass polarizer disclosed herein includes an input/output layer, a first buffer layer positioned above at least a portion of the input/output layer, a layer of epsilon-near-zero (ENZ) material positioned above at least a portion of the first buffer layer, and a metal-containing capping layer positioned above at least a portion of the layer of ENZ material.

公开(公告)号：US10816726B1

公开(公告)日：2020-10-27

申请号：US16549415

申请日：2019-08-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bo Peng ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Thomas Houghton ,  Asli Sahin

IPC: G02B6/34 ,  G02B6/122 ,  G02B6/38 ,  G02B6/36 ,  G02B6/30

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. A waveguide core and a coupler are formed over a layer stack that includes a first dielectric layer and a second dielectric layer over the first dielectric layer. The coupler includes a first plurality of grating structures and a transition structure including a second plurality of grating structures that are positioned between the first plurality of grating structures and the waveguide core. The first plurality of grating structures include respective widths that vary as a function of position relative to the transition structure.

公开(公告)号：US10747030B1

公开(公告)日：2020-08-18

申请号：US16597310

申请日：2019-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02F1/025 ,  G02F1/035

Abstract: Structures for an electro-optic modulator and methods of fabricating a structure for an electro-optic modulator. An electro-optic modulator is positioned proximate to a section of a waveguide core. The electro-optic modulator includes an active layer and a confinement layer. The active layer is composed of a first material, the confinement layer is composed of a second material with a different composition than the first material, the first material has a refractive index that is variable under an applied bias voltage, and the second material has a permittivity with an imaginary part that ranges from 0 to about 15.

公开(公告)号：US10649140B1

公开(公告)日：2020-05-12

申请号：US16291671

申请日：2019-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Abu Thomas

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. A back-end-of-line interconnect structure includes a cap layer, an interlayer dielectric layer, and one or more metal features embedded in the interlayer dielectric layer. The interlayer dielectric layer is stacked in a vertical direction with the cap layer. The one or more metal features have an overlapping arrangement in a lateral direction with the waveguide core, which is arranged under the back-end-of-line interconnect structure.

公开(公告)号：US20200124796A1

公开(公告)日：2020-04-23

申请号：US16165600

申请日：2018-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/136 ,  G02B6/122

Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A first dielectric layer comprised of a first silicon nitride is formed. The waveguide is arranged over the first dielectric layer. A second dielectric layer is formed that is arranged over the waveguide. The second dielectric layer is composed of a second silicon nitride having a lower absorption of optical signals than the first silicon nitride.

公开(公告)号：US10510392B1

公开(公告)日：2019-12-17

申请号：US16047882

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bipul C. Paul ,  Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16

Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.

公开(公告)号：US10436982B1

公开(公告)日：2019-10-08

申请号：US16038868

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/13

Abstract: Structures including waveguide bends, methods of fabricating a structure that includes waveguide bends, and systems that integrate optical components containing different materials. A first waveguide bend is contiguous with a waveguide, and a second waveguide bend is spaced in a vertical direction from the first waveguide bend. The second waveguide bend has an overlapping arrangement with the first waveguide bend in a lateral direction.