公开(公告)号：US11935828B2

公开(公告)日：2024-03-19

申请号：US18116672

申请日：2023-03-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L23/522 ,  H01L21/762 ,  H01L27/08 ,  H01L29/66

CPC classification number: H01L23/5223 ,  H01L21/76224 ,  H01L27/0805 ,  H01L29/66181

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US11830777B2

公开(公告)日：2023-11-28

申请号：US17863137

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Romeric Gay ,  Abderrezak Marzaki

IPC: H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/74 ,  H01L21/04 ,  H01L21/48 ,  H01L21/76

CPC classification number: H01L21/8249 ,  H01L21/04 ,  H01L21/4803 ,  H01L21/74 ,  H01L21/76 ,  H01L27/0623 ,  H01L27/0635 ,  H01L29/732

Abstract: A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

公开(公告)号：US11721646B2

公开(公告)日：2023-08-08

申请号：US17159698

申请日：2021-01-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L27/10 ,  H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01

CPC classification number: H01L23/573 ,  G04F1/005 ,  H01L21/705 ,  H01L27/013 ,  H01L27/101

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US11562933B2

公开(公告)日：2023-01-24

申请号：US16800448

申请日：2020-02-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L21/66 ,  H01L23/00 ,  H03K19/00 ,  H01L29/00

Abstract: A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

公开(公告)号：US11271075B2

公开(公告)日：2022-03-08

申请号：US16802871

申请日：2020-02-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

公开(公告)号：US20210225853A1

公开(公告)日：2021-07-22

申请号：US17220286

申请日：2021-04-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H01L27/1157 ,  G11C5/06 ,  H01L27/11565

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US11069628B2

公开(公告)日：2021-07-20

申请号：US16292958

申请日：2019-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart

IPC: H01L23/02 ,  H01L23/00 ,  G06F21/87 ,  H04N19/44 ,  H01L27/02 ,  G06F21/75

Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

公开(公告)号：US10971578B2

公开(公告)日：2021-04-06

申请号：US16596673

申请日：2019-10-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/283 ,  H01L21/306 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/06 ,  H01L27/10

Abstract: The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.

公开(公告)号：US10943862B2

公开(公告)日：2021-03-09

申请号：US16242529

申请日：2019-01-08

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/94 ,  H01L29/66 ,  H01L27/08

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US10892234B2

公开(公告)日：2021-01-12

申请号：US16154456

申请日：2018-10-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Abderrezak Marzaki

IPC: H01L23/00 ,  G06F21/87 ,  H04L9/00 ,  H01L29/06 ,  G06F21/78 ,  G06F21/55

Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.