公开(公告)号：US20210005612A1

公开(公告)日：2021-01-07

申请号：US17026869

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL ,  Quentin HUBERT ,  Thomas CABOUT

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US20180197963A1

公开(公告)日：2018-07-12

申请号：US15914846

申请日：2018-03-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11524 ,  H01L27/11521 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/306 ,  H01L21/28 ,  G11C16/14

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20180145183A1

公开(公告)日：2018-05-24

申请号：US15852826

申请日：2017-12-22

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc MANTELLI ,  Stephan NIEL ,  Arnaud REGNIER ,  Francesco LA ROSA ,  Julien DELALLEAU

IPC: H01L29/788 ,  G11C16/04 ,  H01L29/66 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/423

CPC classification number: H01L27/11524 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.

公开(公告)号：US20230223332A1

公开(公告)日：2023-07-13

申请号：US18118935

申请日：2023-03-08

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H10B41/35 ,  H01L28/91 ,  H01L28/92

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20190341462A1

公开(公告)日：2019-11-07

申请号：US16513145

申请日：2019-07-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER ,  Julien DELALLEAU

IPC: H01L29/423 ,  H01L29/788 ,  H01L27/11524 ,  G11C16/04 ,  H01L29/78 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/306

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

公开(公告)号：US20190287862A1

公开(公告)日：2019-09-19

申请号：US16429836

申请日：2019-06-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoit FROMENT ,  Stephan NIEL ,  Arnaud REGNIER ,  Abderrezak MARZAKI

IPC: H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  H01L27/08 ,  H01C7/12 ,  H01L21/74 ,  H01L29/8605 ,  H01L29/06 ,  H01L23/522 ,  H01L21/765

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US20190237141A1

公开(公告)日：2019-08-01

申请号：US16256525

申请日：2019-01-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francesco LA ROSA ,  Marc MANTELLI ,  Stephan NIEL ,  Arnaud REGNIER

IPC: G11C16/04 ,  G11C16/14

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.

公开(公告)号：US20190214341A1

公开(公告)日：2019-07-11

申请号：US16242529

申请日：2019-01-08

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak MARZAKI ,  Arnaud REGNIER ,  Stephan NIEL

IPC: H01L23/522 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L23/5223 ,  H01L21/0214 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0805 ,  H01L29/66181 ,  H01L29/945

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

公开(公告)号：US20170178733A1

公开(公告)日：2017-06-22

申请号：US15453663

申请日：2017-03-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER

IPC: G11C16/26 ,  G11C16/08 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11556

CPC classification number: G11C16/26 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/08 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42324

Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.

公开(公告)号：US20150117109A1

公开(公告)日：2015-04-30

申请号：US14528780

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Stephan NIEL ,  Arnaud REGNIER ,  Julien DELALLEAU

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7881

Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

Abstract translation: 本公开涉及包括至少一个字线的存储器，该字线包括一行分离栅极存储单元，每行分离栅极存储单元包括选择晶体管部分，该选择晶体管部分包括选择栅极和包括浮置栅极和控制栅极的浮动栅极晶体管部分。 根据本公开，存储器包括与字线的存储器单元共同的源平面，以在编程期间收集通过存储器单元的编程电流，并且存储器单元的选择晶体管部分连接到源极平面。 编程电流控制电路被配置为通过作用于施加到选择线的选择电压来控制通过存储器单元的编程电流。