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公开(公告)号：US09923566B1
公开(公告)日：2018-03-20
申请号：US15251065
申请日：2016-08-30
Applicant: STMicroelectronics International N.V.
Inventor： Anand Kumar , Gagan Midha
CPC classification number: H03L7/093 , H03C3/095 , H03L7/0891 , H03L7/099 , H03L7/1976 , H04B1/69
Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.
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12.发明授权公开(公告)号：US09793906B1
公开(公告)日：2017-10-17
申请号：US15251570
申请日：2016-08-30
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha
CPC classification number: H03L7/10 , H03L7/083 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/183
Abstract: A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.
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公开(公告)号：US11563436B2
公开(公告)日：2023-01-24
申请号：US17863708
申请日：2022-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee , Anand Kumar , Ankit Gupta
Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.
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公开(公告)号：US11431342B2
公开(公告)日：2022-08-30
申请号：US17521210
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee , Anand Kumar , Ankit Gupta
Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.
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Patent Agency Ranking
公开(公告)号：US10348539B1
公开(公告)日：2019-07-09
申请号：US15919745
申请日：2018-03-13
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha
IPC: H04L27/06 , H04L27/16 , H04L27/00 , H04L27/14 , H04L27/156
Abstract: A frequency demodulated signal includes a frequency modulation in time that is shifted by a DC level corresponding to a carrier frequency offset. A number of different frequency offsets are applied to the frequency demodulated signal to generate a corresponding number of offset frequency demodulated signals. Each offset frequency demodulated signal is correlated against a reference signal and a determination is made as to which correlation produces a highest correlation value. One offset frequency demodulated signal of the number of offset frequency demodulated signals is then selected for output as an offset corrected frequency demodulated signal. The selected signal is the one having the highest correlation value.
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16.发明授权公开(公告)号：US10090845B1
公开(公告)日：2018-10-02
申请号：US15471483
申请日：2017-03-28
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee
Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.
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公开(公告)号：US20180145695A1
公开(公告)日：2018-05-24
申请号：US15356335
申请日：2016-11-18
Applicant: STMicroelectronics International N.V.
Inventor： Abhirup Lahiri , Nitin Gupta , Gagan Midha
CPC classification number: H03L7/093 , H03L7/0802 , H03L7/0893 , H03L7/0895 , H03L7/0896 , H03L7/0991 , H03L7/1976
Abstract: An embodiment circuit includes a first charge pump configured to generate a first current at a first node, and a second charge pump configured to generate a second current at a second node. The circuit further includes an isolation buffer coupled between the first node and the second node and an adder having a first input coupled to the second node. The circuit additionally includes an auxiliary charge pump configured to generate a third current at a second input of the adder, and an oscillator having an input coupled to an output of the adder.
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公开(公告)号：US09331681B2
公开(公告)日：2016-05-03
申请号：US14072373
申请日：2013-11-05
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Archit Joshi
IPC: H03K3/84
CPC classification number: H03K3/84
Abstract: In accordance with an embodiment, a method of generating noise includes generating, using a hardware-based noise generator, a plurality of periodic waveforms having different frequencies, weighting, using the hardware-based noise generator, amplitudes of the plurality of periodic waveforms based on a predetermined spectral shape to form a plurality of weighted waveforms, and summing the plurality of plurality of weighted waveforms to form an output random noise signal.
Abstract translation: 根据实施例，一种产生噪声的方法包括：使用基于硬件的噪声发生器生成具有不同频率的多个周期性波形，使用基于硬件的噪声发生器对多个周期波形的幅度进行加权，基于 预定的光谱形状以形成多个加权波形，并且对多个加权波形进行求和以形成输出随机噪声信号。
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公开(公告)号：US20150123721A1
公开(公告)日：2015-05-07
申请号：US14072373
申请日：2013-11-05
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Archit Joshi
IPC: H03K3/84
CPC classification number: H03K3/84
Abstract: In accordance with an embodiment, a method of generating noise includes generating, using a hardware-based noise generator, a plurality of periodic waveforms having different frequencies, weighting, using the hardware-based noise generator, amplitudes of the plurality of periodic waveforms based on a predetermined spectral shape to form a plurality of weighted waveforms, and summing the plurality of plurality of weighted waveforms to form an output random noise signal.
Abstract translation: 根据实施例，一种产生噪声的方法包括：使用基于硬件的噪声发生器生成具有不同频率的多个周期性波形，使用基于硬件的噪声发生器对多个周期波形的幅度进行加权，基于 预定的光谱形状以形成多个加权波形，并且对多个加权波形进行求和以形成输出随机噪声信号。
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