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公开(公告)号：US09755621B1
公开(公告)日：2017-09-05
申请号：US15162827
申请日：2016-05-24
Applicant: STMicroelectronics International N.V.
Inventor： Rohan Sinha , Vikas Rana
IPC: H03L5/00 , H03K3/356 , H03K19/0185
CPC classification number: H03K3/356113 , H03K19/018521
Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.
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公开(公告)号：US09466347B1
公开(公告)日：2016-10-11
申请号：US14971403
申请日：2015-12-16
Inventor： Marco Pasotti , Vikas Rana
CPC classification number: G11C8/10 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C13/0069
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, a plurality of wordlines coupled to the array of PCM cells, and a row decoder circuit coupled to the plurality of wordlines. The row decoder circuit includes a first low voltage logic gate and a first high voltage level shifter coupled to the first low voltage logic gate. The row decoder circuit also includes a second low voltage logic gate, a second high voltage level shifter coupled to the second low voltage logic gate, and a first low voltage logic circuit coupled to the second low voltage logic gate. In addition, the row decoder circuit includes a second low voltage logic circuit coupled to the second low voltage logic gate, and a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline.
Abstract translation: 集成电路包括相变存储器（PCM）单元的阵列，耦合到PCM单元阵列的多个字线以及耦合到多个字线的行解码器电路。 行解码器电路包括耦合到第一低电压逻辑门的第一低电压逻辑门和第一高电压电平移位器。 行解码器电路还包括第二低电压逻辑门，耦合到第二低电压逻辑门的第二高电压电平移位器和耦合到第二低电压逻辑门的第一低电压逻辑电路。 此外，行解码器电路包括耦合到第二低电压逻辑门的第二低电压逻辑电路和具有耦合到第一和第二低电压逻辑门的输出的输入的低电压字线驱动器，以及耦合到 到一个选定的字线。
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13.发明授权CMOS oscillator having stable frequency with process, temperature, and voltage variation 有权具有稳定频率的CMOS振荡器，具有过程，温度和电压变化公开(公告)号：US09325323B2
公开(公告)日：2016-04-26
申请号：US14474091
申请日：2014-08-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Vikas Rana , Ganesh Raj R
CPC classification number: H03L1/00 , H03K3/011 , H03K3/0315 , H03K3/0322 , H03K3/354 , H03L1/022 , H03L7/0812 , H03L7/0891 , H03L7/0895 , H03L7/093 , H03L7/0995 , H03L7/0997 , H03L7/148 , H03L7/18
Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.
Abstract translation: 时钟信号生成电路，被配置为生成具有在诸如电源电压，温度和处理时间的变化的操作条件的数量的变化中保持的频率的时钟信号。 在一个实施例中，PVT补偿的CMOS环形振荡器的所产生的时钟信号的频率扩展被配置为补偿电源电压的变化，以及通过处理和温度补偿电路对工艺和温度的变化。 PVT补偿的CMOS环形振荡器包括一个稳压电源，用于产生一个电源电压，该电源电压抵抗由于整个电源电压的变化引起的变化。
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公开(公告)号：US11863066B2
公开(公告)日：2024-01-02
申请号：US18168936
申请日：2023-02-14
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US11798603B2
公开(公告)日：2023-10-24
申请号：US18175375
申请日：2023-02-27
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
CPC classification number: G11C7/12 , G11C7/065 , G11C7/222 , G11C11/4091 , G11C11/4094
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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Patent Agency Ranking
公开(公告)号：US11665915B2
公开(公告)日：2023-05-30
申请号：US16863856
申请日：2020-04-30
Inventor： Fabio De Santis , Vikas Rana
IPC: H01L27/105 , H01L27/11521 , H01L27/112 , G11C29/00 , H01L27/11519 , H01L27/11558 , G11C16/04 , H01L21/66
CPC classification number: H01L27/1052 , G11C29/006 , H01L27/1122 , H01L27/1124 , H01L27/11519 , H01L27/11521 , H01L27/11558 , G11C16/0433 , H01L22/00
Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.
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公开(公告)号：US11615823B2
公开(公告)日：2023-03-28
申请号：US17542203
申请日：2021-12-03
Inventor： Vivek Tyagi , Vikas Rana , Chantal Auricchio , Laura Capecchi
IPC: G11C7/12 , G11C7/06 , G11C11/4094 , G11C11/4091 , G11C7/22
Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.
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公开(公告)号：US11611275B2
公开(公告)日：2023-03-21
申请号：US17866372
申请日：2022-07-15
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US11522446B2
公开(公告)日：2022-12-06
申请号：US17494244
申请日：2021-10-05
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
Abstract: The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.
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公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
Inventor： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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