公开(公告)号：US20180061838A1

公开(公告)日：2018-03-01

申请号：US15464537

申请日：2017-03-21

Applicant: STMicroelectronics SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  G11C11/409

CPC classification number: H01L27/10802 ,  G11C11/409 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/7831 ,  H01L29/7841

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US09666577B2

公开(公告)日：2017-05-30

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/66 ,  H01L29/747 ,  H01L29/78 ,  H01L29/423 ,  H01L29/74 ,  H01L29/749 ,  H01L29/10

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

公开(公告)号：US09354391B2

公开(公告)日：2016-05-31

申请号：US14494647

申请日：2014-09-24

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/12 ,  G02B6/122 ,  H01L25/16 ,  H01L27/02 ,  H01L23/60 ,  H01L25/065 ,  H01L23/00

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a second chip is formed in a first chip. The chips may be of the SOI type, with the first chip including a first SOI layer having a first thickness and the second chip including a second SOI layer having a second thickness smaller than the first thickness. The first chip including the component for protecting may include an optical waveguide with the component for protecting formed adjacent the optical waveguide.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护第二芯片的元件的至少一个部件形成在第一芯片中。 芯片可以是SOI型，其中第一芯片包括具有第一厚度的第一SOI层，第二芯片包括第二厚度小于第一厚度的第二SOI层。 包括用于保护的部件的第一芯片可以包括具有邻近光波导形成的用于保护的部件的光波导。

公开(公告)号：US20150061023A1

公开(公告)日：2015-03-05

申请号：US14450597

申请日：2014-08-04

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/66 ,  H01L27/12 ,  H01L29/747 ,  H01L29/78

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.

Abstract translation: 本发明涉及具有静电放电保护装置的IC。 在绝缘层上存在厚度为50nm以下的绝缘绝缘层和第一和第二双极晶体管，一个为npn晶体管，另一个为pnp晶体管。 第一晶体管的基极与第二晶体管的集电极合并，第二晶体管的基极与第一晶体管的集电极合并。 第一和第二双极晶体管被配置为选择性地在保护装置的两个电极之间传导放电电流。 在绝缘层下方存在第一半导体接地层，被电偏压，延伸直到其与第一双极晶体管的基极相连，表现出与第一双极晶体管的基极相同的第一类掺杂，掺杂 密度至少十倍以上。

公开(公告)号：US10312240B2

公开(公告)日：2019-06-04

申请号：US15868901

申请日：2018-01-11

Applicant: STMICROELECTRONICS SA

Inventor： Hassan El Dirani ,  Yohann Solaro ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78 ,  G11C11/409 ,  H01L27/108

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

公开(公告)号：US10062681B2

公开(公告)日：2018-08-28

申请号：US15591565

申请日：2017-05-10

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  Centre National de la Recherche Scientifique

Inventor： Yohann Solaro ,  Sorin Cristoloveanu ,  Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/74 ,  H01L29/749 ,  H01L29/747 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L27/12

CPC classification number: H01L27/0262 ,  H01L27/1203 ,  H01L29/1012 ,  H01L29/42308 ,  H01L29/66477 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7833

Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.

公开(公告)号：US09653476B2

公开(公告)日：2017-05-16

申请号：US13933441

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12 ,  H01L27/02

CPC classification number: H01L27/1203 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it and a ground plane disposed under the layer. A well is disposed under the plane and a first trench is at the periphery of the transistor and extends through the layer into the well. There is a substrate under the well and a p-n diode on a side of the transistor. The diode comprises first and second zones of opposite doping and the first zone is configured for electrical connection to a first electrode of the transistor. The first and second zones are coplanar with the plane and a second trench for separating the first and second zones. The second trench extends through the layer into the plane to a depth less than an interface between the plane and the well. There is a third zone under the second trench forming a junction between the zones.

公开(公告)号：US09530922B2

公开(公告)日：2016-12-27

申请号：US14496192

申请日：2014-09-25

Applicant: STMICROELECTRONICS SA

Inventor： Pascal Fonteneau

IPC: H01L31/111 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/11 ,  H01L31/02 ,  H01L27/12 ,  H01L31/028 ,  H01L31/105

CPC classification number: H01L31/1113 ,  H01L27/1203 ,  H01L31/02019 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/105 ,  H01L31/11 ,  H01L31/18 ,  Y02E10/547

Abstract: An overvoltage protection component may be in a SOI layer, a portion of the SOI layer forming the core of an optical waveguide. This component may be made of semiconductor regions of different doping types and/or levels, at least one of these regions corresponding to at least a portion of the waveguide core.

Abstract translation: 过电压保护组件可以在SOI层中，SOI层的一部分形成光波导的核心。 该组件可以由不同掺杂类型和/或电平的半导体区域制成，这些区域中的至少一个对应于波导芯的至少一部分。

公开(公告)号：US20160238806A1

公开(公告)日：2016-08-18

申请号：US15140701

申请日：2016-04-28

Applicant: STMicroelectronics SA

Inventor： Pascal Fonteneau

IPC: G02B6/42 ,  H01L23/528 ,  H01L23/498 ,  H01L27/02 ,  H01L29/87 ,  G02B6/122 ,  H01L25/16

CPC classification number: G02B6/4275 ,  G02B6/122 ,  G02B6/428 ,  G02B2006/12061 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/60 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/167 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/87 ,  H01L2224/16235 ,  H01L2225/06534 ,  H01L2225/06572 ,  H01L2924/10253 ,  H01L2924/1431

Abstract: A device includes integrated circuit chips mounted on one another. At least one component for protecting elements of a first one of the chips is formed in a second one of the chips. Preferably, the chips are of SOI type, the second chip includes an SOI layer having a first thickness sufficient to support the component for protecting elements. The first chip also includes an SOI layer but having a second thickness smaller than the first thickness that is insufficient to support the component for protecting elements. The SOI layer of the second chip may be an optical waveguide layer.

Abstract translation: 一种装置包括彼此安装的集成电路芯片。 用于保护芯片中的第一芯片的元件的至少一个部件形成在第二芯片中。 优选地，芯片是SOI型的，第二芯片包括具有足以支撑用于保护元件的部件的第一厚度的SOI层。 第一芯片还包括SOI层，但是具有小于不足以支撑用于保护元件的部件的第一厚度的第二厚度。 第二芯片的SOI层可以是光波导层。

公开(公告)号：US09337302B2

公开(公告)日：2016-05-10

申请号：US13933379

申请日：2013-07-02

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L29/66 ,  H01L27/02 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L29/66477 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

Abstract: An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.

Abstract translation: 集成电路具有FET，具有FET的UTBOX层铅垂，具有FET的栅极和沟道的第一掺杂铅垂的下层接地层，第一和第二下层半导体元件，两者均与漏极或源极接触，电极分别接触 接地平面和第一元件，一个具有第一掺杂并且连接到第一电压，另一个具有第一掺杂并且连接到不同于第一掺杂的第二偏置电压，具有第二掺杂和铅垂的半导体阱与 第一接地平面和两个元件，第一沟槽将第一FET与集成电路的其它部件隔离并延伸穿过该阱进入阱，第二和第三沟槽将FET与电极隔离，并延伸至小于 平面/井界面。