公开(公告)号：US5512847A

公开(公告)日：1996-04-30

申请号：US321012

申请日：1994-10-06

申请人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

发明人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/01

CPC分类号： H03K19/09448 ,  H03K19/017518 ,  H03K19/01806 ,  H03K19/09425 ,  H03K19/09429 ,  H01L2924/0002

摘要： In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

摘要翻译： 在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。 因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。 类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由 双极晶体管。 因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

公开(公告)号：US4443812A

公开(公告)日：1984-04-17

申请号：US231285

申请日：1981-02-04

申请人： Ichiro Imaizumi ,  Masatoshi Kimura ,  Shikayuki Ochi ,  Masayoshi Yoshimura ,  Takashi Yamaguchi ,  Toyomasa Koda

发明人： Ichiro Imaizumi ,  Masatoshi Kimura ,  Shikayuki Ochi ,  Masayoshi Yoshimura ,  Takashi Yamaguchi ,  Toyomasa Koda

IPC分类号： H01L21/331 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/73 ,  H01L29/8605 ,  H01L29/44 ,  H01L29/72

CPC分类号： H01L29/402 ,  H01L27/04 ,  H01L29/0821 ,  H01L29/8605 ,  H02B13/02 ,  Y10S257/913

摘要： A high-breakdown-voltage semiconductor device wherein a resistor body made of a P-type impurity region is disposed in a surface region of an N-type semiconductor body so as to form a resistor element, a P-type low doped region is disposed around the resistor body, and a plate layer which extends from a high potential electrode of the resistor body covers a main part of the P-type low doped region.

摘要翻译： 将由P型杂质区构成的电阻体设置在N型半导体本体的表面区域中以形成电阻元件的高耐压半导体器件，设置P型低掺杂区域 并且从电阻体的高电位电极延伸的板层覆盖P型低掺杂区域的主要部分。

公开(公告)号：US4024568A

公开(公告)日：1977-05-17

申请号：US617809

申请日：1975-09-29

申请人： Masayoshi Yoshimura

发明人： Masayoshi Yoshimura

IPC分类号： H01L29/417 ,  H01L21/331 ,  H01L23/482 ,  H01L29/08 ,  H01L29/73 ,  H01L23/48 ,  H01L27/10 ,  H01L29/34 ,  H01L29/72

CPC分类号： H01L29/0804 ,  H01L23/4824 ,  H01L2924/0002

摘要： In a transistor wherein a second conductivity type region is formed surrounding a first conductivity type region in a principal surface electrodes are formed on a surface of the first conductivity type region, an electrode of the second conductivity type region is formed in a manner to encircle the first-mentioned electrodes, and electrodes of the first conductivity type region are led outside the electrode of the second conductivity type region through an insulating film, whereby concentration of current is prevented.

摘要翻译： 在第一导电类型区域的表面上形成有在主表面电极周围形成围绕第一导电类型区域的第二导电类型区域的晶体管，以包围第一导电类型区域的方式形成第二导电类型区域的电极 首先提到的电极和第一导电类型区域的电极通过绝缘膜被引导到第二导电类型区域的电极外面，从而防止电流集中。

公开(公告)号：US06708315B2

公开(公告)日：2004-03-16

申请号：US09789524

申请日：2001-02-22

申请人： Toshinori Hosokawa ,  Masayoshi Yoshimura

发明人： Toshinori Hosokawa ,  Masayoshi Yoshimura

IPC分类号： G06F1750

CPC分类号： G01R31/3181

摘要： A design for testability is applied so as to enable significant reduction in test time of an actual integrated circuit. First, an integrated circuit is full-scan designed on a block-by-block basis and test input patterns are generated (S11). Then, one of the blocks to which the design for testability has not been allocated is selected (S12), and a full-scan design is allocated thereto (S14). Test points are inserted into a block that has more than a prescribed number of parallel test input patterns when that block is full-scan designed (YES in S15) (S16).

摘要翻译： 应用可测试性的设计，以便能够显着降低实际集成电路的测试时间。 首先，逐块地设计集成电路，并生成测试输入模式（S11）。 然后，选择其中尚未分配用于可测试性设计的块之一（S12），并且分配全扫描设计（S14）。 当该块被全扫描设计时（S15中为“是”），将测试点插入具有超过规定数量的并行测试输入模式的块中（S16）。

公开(公告)号：US4983862A

公开(公告)日：1991-01-08

申请号：US429489

申请日：1989-10-31

申请人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

发明人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/177

CPC分类号： H03K19/09448 ,  H03K19/017518 ,  H03K19/01806 ,  H03K19/09425 ,  H03K19/09429 ,  H01L2924/0002

摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

公开(公告)号：US4879480A

公开(公告)日：1989-11-07

申请号：US240450

申请日：1988-09-02

申请人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akiro Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

发明人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akiro Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/177

CPC分类号： H03K19/09448 ,  H03K19/017518 ,  H03K19/01806 ,  H03K19/09425 ,  H03K19/09429 ,  H01L2924/0002

摘要： In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

摘要翻译： 在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。 因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。 类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由 双极晶体管。 因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

公开(公告)号：US4095253A

公开(公告)日：1978-06-13

申请号：US744397

申请日：1976-11-23

申请人： Masayoshi Yoshimura ,  Keizo Otsuki ,  Senji Shoji ,  Tomio Yamada ,  Ichio Shimizu ,  Yuji Arai

发明人： Masayoshi Yoshimura ,  Keizo Otsuki ,  Senji Shoji ,  Tomio Yamada ,  Ichio Shimizu ,  Yuji Arai

IPC分类号： H01L23/28 ,  H01L23/495 ,  H01L23/38 ,  H01L23/42 ,  H01L23/44

CPC分类号： H01L23/49568 ,  H01L23/49541 ,  H01L2924/0002

摘要： A single in-line, high power, resin-packaged semiconductor device having a plurality of external leads disposed in parallel to each other and projecting from one side surface of a resin-molded package, wherein a heat sink fin mounting plate is formed in unitary structure with a plate for carrying a semiconductor pellet and arranged to project from a recessed portion of the opposite side surface of the resin-molded package and a heat sink fin has one end bent in U-shape and caulked on the fin mounting plate and the remaining portion overlapping one principal surface of the resin-molded package. The projection of the heat sink fin from the resin-molded package can be reduced to enable the device to be assembled in compact electronic instruments or devices. Heat dissipation efficiency can also be improved by mounting the semiconductor device on a chassis with the heat sink fin brought in contact with the chassis.

公开(公告)号：US4056413A

公开(公告)日：1977-11-01

申请号：US729710

申请日：1976-10-05

申请人： Masayoshi Yoshimura

发明人： Masayoshi Yoshimura

IPC分类号： H01L21/306 ,  H01L21/74 ,  H01L21/761 ,  H01L21/302 ,  H01L21/20 ,  H01L21/76

CPC分类号： H01L21/30608 ,  H01L21/74 ,  H01L21/761

摘要： An epitaxial silicon layer is grown on a principal surface of the (100) crystal face of a silicon single crystal having a depressed portion in the principal surface. The epitaxial silicon layer is flattened by etching, the epitaxial silicon layer being formed to a sufficient thickness so that the side surfaces of the crystal face (111) of a new depressed portion as viewed in a vertical section (the new depressed portion being formed in a surface of the epitaxial silicon layer in correspondence with the first-mentioned depressed portion) intersect at a level which is, at the lowest, the final plane of the etching. The etching is anisotropic etching with an alkali etchant, by which the epitaxial silicon layer is etched down to the final plane.

公开(公告)号：US4689503A

公开(公告)日：1987-08-25

申请号：US575567

申请日：1984-01-31

申请人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

发明人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/01 ,  H03K19/013 ,  H03K19/017

CPC分类号： H03K19/09448 ,  H03K19/017518 ,  H03K19/01806 ,  H03K19/09425 ,  H03K19/09429 ,  H01L2924/0002

摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

摘要翻译： 在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。 因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。 类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由 双极晶体管。 因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

公开(公告)号：US4423433A

公开(公告)日：1983-12-27

申请号：US156015

申请日：1980-06-03

申请人： Ichiro Imaizumi ,  Shikayuki Ochi ,  Masatoshi Kimura ,  Masayoshi Yoshimura ,  Takashi Yamaguchi ,  Toyomasa Koda

发明人： Ichiro Imaizumi ,  Shikayuki Ochi ,  Masatoshi Kimura ,  Masayoshi Yoshimura ,  Takashi Yamaguchi ,  Toyomasa Koda

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/41 ,  H01L29/8605 ,  H01L27/02

CPC分类号： H01L29/8605

摘要： A high-breakdown-voltage resistance element comprises a semiconductor body, an impurity layer disposed in a surface region of the semiconductor body to provide a resistor body, a first electrode connected to one end of the resistor body through a contact hole in a first insulating film formed on the surface of the semiconductor body, and a second electrode connected to the other end of the resistor body through another contact hole in the insulating film. A second insulating film is formed on the first and second electrodes, and a third electrode is connected to the first electrode through a contact hole in the second insulating film, so that the entire surface of the resistor body and adjacent areas are covered with the first, second and third electrodes.

摘要翻译： 高耐压电阻元件包括半导体本体，设置在半导体本体的表面区域中以提供电阻体的杂质层，通过第一绝缘体中的接触孔与电阻体的一端连接的第一电极 形成在半导体本体的表面上的膜，以及通过绝缘膜中的另一接触孔与电阻体的另一端连接的第二电极。 第二绝缘膜形成在第一和第二电极上，第三电极通过第二绝缘膜中的接触孔连接到第一电极，使得电阻体和相邻区域的整个表面被第一电极 ，第二和第三电极。