公开(公告)号：US20190157200A1

公开(公告)日：2019-05-23

申请号：US15939211

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Harsono Simka

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

公开(公告)号：US20190131451A1

公开(公告)日：2019-05-02

申请号：US15872455

申请日：2018-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde

IPC: H01L29/78 ,  H01L21/768

Abstract: A method provides a source-drain stressor for a semiconductor device including source and drain regions. Recesses are formed in the source and drain regions. An insulating layer covers the source and drain regions. The recesses extend through the insulating layer above the source and drain regions. An intimate mixture layer of materials A and B is provided. Portions of the intimate mixture layer are in the recesses. The portions of the intimate mixture layer have a height and a width. The height divided by the width is greater than three. A top surface of the portions of the intimate mixture layer in the recesses is free. The intimate mixture layer is reacted to form a reacted intimate mixture layer including a compound AxBy. The compound AxBy occupies less volume than a corresponding portion of the intimate mixture layer.

公开(公告)号：US20180300618A1

公开(公告)日：2018-10-18

申请号：US15678050

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan Hatcher

IPC: G06N3/063 ,  H01L27/112 ,  G06N3/04

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

公开(公告)号：US09978833B2

公开(公告)日：2018-05-22

申请号：US15289951

申请日：2016-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/84

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/786

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

公开(公告)号：US09941405B2

公开(公告)日：2018-04-10

申请号：US15340951

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/306 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/417 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

公开(公告)号：US09871139B2

公开(公告)日：2018-01-16

申请号：US15342003

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

公开(公告)号：US20170345932A1

公开(公告)日：2017-11-30

申请号：US15342008

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Chris Bowen ,  Kiyotaka Imai ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

公开(公告)号：US20170271514A1

公开(公告)日：2017-09-21

申请号：US15340951

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L29/165 ,  H01L29/06 ,  H01L21/3213

CPC classification number: H01L29/7848 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

公开(公告)号：US09431492B2

公开(公告)日：2016-08-30

申请号：US14628541

申请日：2015-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/45 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion.

Abstract translation: 提供了包括触点的集成电路装置及其形成方法。 器件可以包括衬底上的翅片，翅片上的栅极结构和栅极结构侧的鳍中的源极/漏极区域。 所述装置还可以包括覆盖源极/漏极区域的最上表面和栅极结构的侧壁的接触插塞。 接触插塞可以包括包括第一材料的内部部分和包括不同于第一材料的第二材料的外部部分。 外部部分可以至少部分地覆盖内部部分的侧壁，并且外部部分的一部分可以设置在门结构的侧壁和内部部分的侧壁之间。

公开(公告)号：US20160133745A1

公开(公告)日：2016-05-12

申请号：US14934045

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L21/768

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/743 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7848

Abstract: Exemplary embodiments provide methods and systems for fabricating a metal source-drain stressor in a MOS device channel having improved tensile stress. Aspects of exemplary embodiment include forming a recess in source and drain areas; forming a metal contact layer on surfaces of the recess that achieves low contact resistivity; forming a metallic diffusion barrier over the metal contact layer; forming a layer M as an intimate mixture of materials A and B that substantially fills the recess; capping the layer M with a capping layer so that layer M is fully encapsulated and the capping layer prevents diffusion of A and B; and forming a compound AxBy within the layer M via a thermal reaction resulting in a reacted layer M comprising the metal source-drain stressor.

Abstract translation: 示例性实施例提供了在具有改善的拉伸应力的MOS器件通道中制造金属源极 - 漏极应力器的方法和系统。 示例性实施例的方面包括在源极和漏极区域中形成凹部; 在凹陷的表面上形成接触电阻率低的金属接触层; 在金属接触层上形成金属扩散阻挡层; 形成层M作为基本上填充凹部的材料A和B的紧密混合物; 用覆盖层覆盖层M，使得层M被完全封装，并且覆盖层防止A和B的扩散; 以及通过热反应在层M内形成化合物AxBy，导致包含金属源 - 漏应力源的反应层M。