公开(公告)号：US20160071970A1

公开(公告)日：2016-03-10

申请号：US14625376

申请日：2015-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Robert C. Bowen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

Abstract: Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal.

Abstract translation: 公开了用于半金属晶体管的示例性实施例，包括：与金属接触相邻的半金属接触区域; 至少一个半导体端子; 以及连接在所述接触区域和所述半导体端子之间的半金属过渡区域，所述半金属过渡区域从从所述接触区域的界面开始的半金属基本上为零的间隙向具有朝向所述半导体端子的能带隙的半导体转变。

公开(公告)号：US11816563B2

公开(公告)日：2023-11-14

申请号：US16409487

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

IPC: G06F11/07 ,  G06F11/10 ,  G06N3/08 ,  G06F17/16

CPC classification number: G06N3/08 ,  G06F17/16

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

公开(公告)号：US20200234114A1

公开(公告)日：2020-07-23

申请号：US16409487

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

IPC: G06N3/08 ,  G06F17/16

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

公开(公告)号：US10585630B2

公开(公告)日：2020-03-10

申请号：US15845985

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Vladimir Nikitin ,  Dmytro Apalkov

IPC: H01L21/822 ,  H01L27/22 ,  G06F3/06 ,  H01L27/11578 ,  H01L21/3105 ,  G11C11/16 ,  G11C11/18 ,  H01L43/08

Abstract: A memory device and method for providing the memory device are described. The memory device includes word lines, a first plurality of bit lines, a second plurality of bit lines and selectorless memory cells. Each selectorless memory cell is coupled with a word line, a first bit line of the first plurality of bit lines and a second bit line of the second plurality of bit lines. The selectorless memory cell includes first and second magnetic junctions. The first and second magnetic junctions are each programmable using a spin-orbit interaction torque. The word line is coupled between the first and second magnetic junctions. The first and second bit lines are coupled with the first and second magnetic junctions, respectively. The selectorless memory cell is selected for a write operation based on voltages in the word line, the first bit line and the second bit line.

公开(公告)号：US20190332943A1

公开(公告)日：2019-10-31

申请号：US16122789

申请日：2018-09-05

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan M. Hatcher

IPC: G06N3/08 ,  G06N3/04 ,  G06N5/04

Abstract: A method and system for training a neural network are described. The method includes providing at least one continuously differentiable model of the neural network. The at least one continuously differentiable model is specific to hardware of the neural network. The method also includes iteratively training the neural network using the at least one continuously differentiable model to provide at least one output for the neural network. Each iteration uses at least one output of a previous iteration and a current continuously differentiable model of the at least one continuously differentiable model.

公开(公告)号：US20190154493A1

公开(公告)日：2019-05-23

申请号：US15886753

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G01G23/38 ,  G11C7/10 ,  G06G7/16 ,  G11C13/00

Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

公开(公告)号：US10164121B2

公开(公告)日：2018-12-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

公开(公告)号：US20170148922A1

公开(公告)日：2017-05-25

申请号：US15181327

申请日：2016-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Borna J. Obradovic ,  Joon Goo Hong ,  Rwik Sengupta

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78645

Abstract: A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.

公开(公告)号：US20160071729A1

公开(公告)日：2016-03-10

申请号：US14830622

申请日：2015-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02474 ,  H01L21/02477 ,  H01L21/02483 ,  H01L21/02485 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02538 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: Exemplary embodiments provide methods for fabricating a nanosheet structure suitable for field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure; growing a stack of alternating layers of active and sacrificial materials over the substrate; and selectively etching the sacrificial material, wherein due to the properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and substantially a same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow.

Abstract translation: 示例性实施例提供了制造适用于场效应晶体管（FET）制造的纳米片结构的方法。 示例性实施方案的方面包括选择将用作纳米片结构中的通道材料的活性材料，适于活性材料的外延生长的基底和在纳米片结构的制造期间使用的牺牲材料; 在衬底上生长一叠交替的活性和牺牲材料层; 并且选择性地蚀刻牺牲材料，其中由于牺牲材料的性质，选择性蚀刻导致活性材料的剩余层具有大于1的纵横比和基本上相同的厚度和原子平滑度沿着整个横截面宽度 每个活性物质层垂直于电流。

公开(公告)号：US11574193B2

公开(公告)日：2023-02-07

申请号：US16122789

申请日：2018-09-05

Applicant: Samsung Electronics Co., LTD.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Jorge A. Kittl ,  Ryan M. Hatcher

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/04

Abstract: A method and system for training a neural network are described. The method includes providing at least one continuously differentiable model of the neural network. The at least one continuously differentiable model is specific to hardware of the neural network. The method also includes iteratively training the neural network using the at least one continuously differentiable model to provide at least one output for the neural network. Each iteration uses at least one output of a previous iteration and a current continuously differentiable model of the at least one continuously differentiable model.