公开(公告)号：US20240133683A1

公开(公告)日：2024-04-25

申请号：US18460929

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho KWAK ,  Jinsun KIM ,  Moosong LEE ,  Seungyoon LEE ,  Jeongjin LEE ,  Chan HWANG ,  Dohyeon PARK ,  Yeeun HAN

IPC: G01B15/00

CPC classification number: G01B15/00

Abstract: In an overlay measurement method, an overlay mark having programmed overlay values is provided. The overlay mark is scanned with an electron beam to obtain a voltage contrast image. A defect function that changes according to the overlay value is obtained from voltage contrast image data. Self-cross correlation is performed on the defect function to determine an overlay.

公开(公告)号：US20220181146A1

公开(公告)日：2022-06-09

申请号：US17358346

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sookyung KIM ,  Chan HWANG

IPC: H01L21/027 ,  G03F7/20 ,  G03F1/22

Abstract: A method of manufacturing an integrated circuit (IC) device, the method including forming an underlayer on a feature layer such that the underlayer includes an acid generator; forming an acid-containing underlayer by generating a first acid from the acid generator; forming a photoresist film on the acid-containing underlayer; generating a second acid in a first area of the photoresist film by exposing the first area of the photoresist film; diffusing the first acid from the acid-containing underlayer into the first area of the photoresist film; and forming a photoresist pattern by developing the photoresist film.

公开(公告)号：US20220082926A1

公开(公告)日：2022-03-17

申请号：US17308484

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soonmok HA ,  Jaehee KIM ,  Sangho YUN ,  Chan HWANG

IPC: G03F1/24

Abstract: An EUV photomask having a main area and a scribe lane area and reflecting EUV light includes a reflective multilayer film and an absorption pattern, wherein the scribe lane area includes first and second lanes, wherein the first lane includes first and second sub-lanes extending in the same direction as an extending direction of the first lane, wherein the first sub-lane includes a first dummy pattern that is a portion of the absorption pattern, and the second sub-lane includes a second dummy pattern that is a portion of the absorption pattern, and when EUV light that is not absorbed by the first and second dummy patterns and is reflected by the reflective multilayer film is irradiated at least twice by overlapping a negative tone photoresist, an amount of light exceeds a threshold dose of light in the negative tone photoresist corresponding to the first lane.

公开(公告)号：US20240152043A1

公开(公告)日：2024-05-09

申请号：US18381731

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minseung SONG ,  Janghoon KIM ,  Sangho YUN ,  Chan HWANG

IPC: G03F1/22 ,  G03F1/70 ,  G03F1/80 ,  G03F7/00

CPC classification number: G03F1/22 ,  G03F1/70 ,  G03F1/80 ,  G03F7/70616

Abstract: A method of manufacturing an extreme ultraviolet mask including preparing a preliminary layout, forming a plurality of preliminary target patterns by using a plurality of preliminary spacer patterns formed by using the preliminary layout, evaluating presence or absence of an abnormal target pattern among the plurality of preliminary target patterns, preparing a layout configured to form a plurality of spacer patterns by modifying the preliminary layout when the plurality of preliminary target patterns include the abnormal target pattern, and manufacturing an extreme ultraviolet mask with the layout to form a plurality of target patterns by using the plurality of spacer patterns, wherein, the plurality of preliminary spacer patterns extend in one direction.

公开(公告)号：US20220066328A1

公开(公告)日：2022-03-03

申请号：US17234908

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soon Hwan CHA ,  Chan HWANG ,  Woo Jin JUNG

IPC: G03F7/20

Abstract: A semiconductor device manufacturing system includes a photolithography apparatus that performs exposure. On a semiconductor substrate including a chip area and a scribe lane area. An etching apparatus etches the exposed semiconductor substrate. An observing apparatus images the etched semiconductor substrate. A controller controls the photolithography apparatus and the etching apparatus. The controller generates a first mask pattern and provides the first mask pattern to the photolithography apparatus. The photolithography apparatus performs exposure on the semiconductor substrate using the first mask pattern. The etching apparatus performs etching on the exposed semiconductor substrate to provide an etched semiconductor substrate. The observing apparatus generates a first semiconductor substrate image by imaging the etched semiconductor substrate corresponding to the scribe lane area. The controller generates a second mask pattern based on the first mask pattern and the first semiconductor substrate image, and provides the second mask pattern to the photolithography apparatus.

公开(公告)号：US20200152638A1

公开(公告)日：2020-05-14

申请号：US16745956

申请日：2020-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon-mok HA ,  Jae-hee KIM ,  Chan HWANG ,  Jong-hyuk KIM

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/027 ,  H01L21/311

Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.

公开(公告)号：US20170261317A1

公开(公告)日：2017-09-14

申请号：US15448325

申请日：2017-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon LEE ,  Chan HWANG ,  Jeong Jin LEE

IPC: G01B11/27 ,  G01B11/00

CPC classification number: G01B11/272 ,  G01B11/002 ,  G03F9/7084 ,  H01L2224/16145

Abstract: A method for measuring wafer alignment is provided. The method includes providing a plurality of first mark patterns extending in a first direction on a wafer, providing at least one second mark pattern on the first mark patterns such that it overlaps and intersects the first mark patterns, irradiating an optical signal onto the first mark patterns and the second mark pattern and obtaining coordinates of the second mark pattern by detecting signals from the second mark pattern.

公开(公告)号：US20240234332A1

公开(公告)日：2024-07-11

申请号：US18489354

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junseok PARK ,  Seunghak PARK ,  Chan HWANG

IPC: H01L23/544 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/544 ,  H10B41/27 ,  H10B43/27 ,  H01L2223/54426

Abstract: A semiconductor device includes a first stack structure in a first region, a first channel structure in contact with the substrate, a second stack structure on the first stack structure, a second channel structure connected to the first channel structure, a third stack structure on the second stack structure, a third channel structure connected to the second channel structure, a first mold structure in a second region, first overlay structures on the first mold structure, a second mold structure on the first mold structure, second overlay structures on the second mold structure, a third mold structure on the second mold structure, and third overlay structures on the third mold structure, wherein the first to third overlay structures are on an overlay mark region, and the first to third overlay structures are in at least one of quadrants in the overlay mark region.

公开(公告)号：US20240152046A1

公开(公告)日：2024-05-09

申请号：US18218246

申请日：2023-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongjin LEE ,  Doogyu LEE ,  Seungyoon LEE ,  Chan HWANG

IPC: G03F1/70 ,  G03F7/00 ,  G03F7/20

CPC classification number: G03F1/70 ,  G03F7/2004 ,  G03F7/70033 ,  G03F7/70558

Abstract: A method of controlling semiconductor process includes forming a plurality of sample overlay keys by irradiating a first dose of extreme ultraviolet (EUV) light to a first photoresist layer formed on at least one sample wafer; determining a sample correction parameter for correcting a sample overlay error measured from the plurality of sample overlay keys; updating the sample correction parameter based on a difference between the first dose and a second dose; forming a plurality of main overlay keys by irradiating a second dose of extreme ultraviolet light to a second photoresist layer formed on the sample wafer based on the updated sample correction parameter; determining the main correction parameter based on a main overlay error measured from the plurality of main overlay keys; and performing a photolithography process on a wafer different from the sample wafer based on the main correction parameter.

公开(公告)号：US20240045336A1

公开(公告)日：2024-02-08

申请号：US18133118

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sookyung KIM ,  Chan HWANG ,  Jonghyun JUNG ,  Moosong LEE

IPC: G03F7/20 ,  G03F7/004

CPC classification number: G03F7/2004 ,  G03F7/2022 ,  G03F7/0045

Abstract: A method for forming a resist pattern is disclosed. According to the method, a photosensitive layer is formed on a substrate by using an inorganic photoresist. The photosensitive layer is irradiated with a deep ultraviolet (DUV) light. The photosensitive layer is irradiated with an extreme ultraviolet (EUV) light after the irradiation of the DUV light. The photosensitive layer exposed to the EUV light is heated. The heated photosensitive layer is developed.