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    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    13.
    发明公开
    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230162766A1

    公开(公告)日：2023-05-25

    申请号：US17951567

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngmin Jo ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222

    Abstract: A memory system includes a plurality of memory devices, each connected to internal channels respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller connected to an external channel including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit connecting the external channel to each of the internal channels. The interface circuit is configured to perform channel conversion by serializing a parallel data signal received from the controller through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.

    Impedance calibration circuit and method of calibrating impedance in memory device
    14.
    发明授权
    Impedance calibration circuit and method of calibrating impedance in memory device 有权

    公开(公告)号：US11367471B2

    公开(公告)日：2022-06-21

    申请号：US17352527

    申请日：2021-06-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Tongsung Kim ,  Chiweon Yoon ,  Byunghoon Jeong

    IPC: G11C7/10 ,  H03K19/00 ,  H01L27/115 ,  G11C16/04

    Abstract: An impedance calibration circuit includes a first variable impedance, a second variable impedance, a third variable impedance. The first variable impedance is connected to a ZQ terminal. A first control circuit performs a first impedance calibration on the first variable impedance based on an output signal from an output of a first comparator. A second control circuit performs a second impedance calibration on the third variable impedance based on an output signal from an output of a second comparator. A first switch connects an input of the first comparator to one of the ZQ terminal and the first node. A second switch connects the output of the first comparator to one of the first and second control circuits. A third switch connects an output of the first switch to one of first and second input terminals of the first comparator and connects the reference voltage to the other.

    MEMORY DEVICE INCLUDING MULTIPLE MEMORY CHIPS AND DATA SIGNAL LINES AND A METHOD OF OPERATING THE MEMORY DEVICE
    15.
    发明申请
    MEMORY DEVICE INCLUDING MULTIPLE MEMORY CHIPS AND DATA SIGNAL LINES AND A METHOD OF OPERATING THE MEMORY DEVICE 有权

    公开(公告)号：US20220101894A1

    公开(公告)日：2022-03-31

    申请号：US17410210

    申请日：2021-08-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seonkyoo Lee ,  Chiweon Yoon ,  Byunghoon Jeong ,  Youngmin Jo

    IPC: G11C7/10 ,  H01L25/065

    Abstract: An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.

    CLOCK SIGNAL GENERATOR AND OPERATING METHOD THEREOF
    16.
    发明公开
    CLOCK SIGNAL GENERATOR AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240267034A1

    公开(公告)日：2024-08-08

    申请号：US18416527

    申请日：2024-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jihyun Park ,  Bilal Ahmad Janjua ,  Chiweon Yoon ,  Jungyu Lee

    IPC: H03K3/011 ,  G05F1/46 ,  G05F3/26 ,  H03K3/0233

    CPC classification number: H03K3/011 ,  G05F1/468 ,  G05F3/262 ,  H03K3/0233

    Abstract: A method of generating clock signals includes: receiving a bandgap reference voltage from a bandgap reference circuit; generating a first current having a first curvature characteristic based on the bandgap reference voltage; generating a second current having a second curvature characteristic based on the bandgap reference voltage; generating a first complementary to absolute temperature (CTAT) current by adding the first current to the second current; receiving a temperature-variable voltage and a temperature-fixed voltage from a voltage generator; generating an offset current based on the temperature-variable voltage and the temperature-fixed voltage; generating a reference current by adding the first CTAT current to the offset current; and generating the clock signals by alternately discharging a first capacitor and a second capacitor based on the reference current, and charging the first capacitor and the second capacitor based on a power voltage.

    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM
    17.
    发明公开
    MEMORY SYSTEM, OPERATING METHOD OF THE MEMORY SYSTEM, AND INTERFACE CIRCUIT OF THE MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240257850A1

    公开(公告)日：2024-08-01

    申请号：US18426825

    申请日：2024-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Youngmin Jo ,  Jungjune Park ,  Chiweon Yoon

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/225 ,  G11C7/1096 ,  G11C7/222

    Abstract: Provided is a memory system including a memory device including a plurality of non-volatile memories, each of the plurality of non-volatile memories being electrically connected to a buffer chip, and a memory controller electrically connected to the buffer chip and configured to transmit a reference clock signal used in correction of a data signal, wherein the buffer chip includes a delay clock generation chain configured to generate a first delay clock signal or a second delay clock signal from the reference clock signal, a first register configured to store the first delay clock signal, and a second register configured to store the second delay clock signal, and wherein the buffer chip is configured to perform compensation on a strobe signal of the data signal based on the first delay clock signal, and perform compensation on the data signal based on the second delay clock signal.

    MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE
    19.
    发明公开
    MEMORY PACKAGE, SEMICONDUCTOR DEVICE, AND STORAGE DEVICE 审中-公开

    公开(公告)号：US20230179193A1

    公开(公告)日：2023-06-08

    申请号：US17866517

    申请日：2022-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

    IPC: H03K5/14 ,  H03K5/135 ,  H03L7/081

    CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

    Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

    Nonvolatile memory device and storage device including the nonvolatile memory device
    20.
    发明授权
    Nonvolatile memory device and storage device including the nonvolatile memory device 有权

    公开(公告)号：US11594287B2

    公开(公告)日：2023-02-28

    申请号：US17198382

    申请日：2021-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon

    IPC: G11C16/32 ,  G11C16/04 ,  H01L25/065

    Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

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