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    Semiconductor memory devices and memory systems including the same
    12.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权
    半导体存储器件和包括其的存储器系统

    公开(公告)号：US09390778B2

    公开(公告)日：2016-07-12

    申请号：US14798164

    申请日：2015-07-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su-A Kim ,  Dae-Sun Kim ,  Dae-Jeong Kim ,  Sung-Min Ryu ,  Kwang-Il Park ,  Chul-Woo Park ,  Young-Soo Sohn ,  Jae-Youn Youn

    IPC: G11C8/12 ,  G11C8/08 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

    CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4097

    Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

    Abstract translation: 半导体存储器件包括存储单元阵列，子字线驱动器和功率选择开关。 存储单元阵列包括耦合到字线的存储单元行。 子字线驱动器耦合到字线。 功率选择开关耦合到子字线驱动器。 每个电源选择开关控制从字线激活的第一字线的去激活电压电平和与第一字线相邻的第二字线的截止电压电平，使得去激活电压电平和截止电压电平 具有接地电压，第一负电压和第二负电压中的至少一个。 接地电压，第一负电压和第二负电压彼此具有不同的电压电平。

    Semiconductor memory device and refresh leveraging driving method thereof
    16.
    发明授权
    Semiconductor memory device and refresh leveraging driving method thereof 有权
    半导体存储器件及其更新利用驱动方法

    公开(公告)号：US08988964B2

    公开(公告)日：2015-03-24

    申请号：US14071757

    申请日：2013-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Jeong Kim ,  Kabyong Kim ,  Kwang-Woo Lee ,  Heon Lee ,  Inho Cho

    IPC: G11C7/22 ,  G11C11/406 ,  G11C16/34 ,  G11C29/00

    CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C16/3418 ,  G11C29/82 ,  G11C2211/4063

    Abstract: A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

    Abstract translation: 提供了一种刷新利用驱动方法，其包括将刷新利用操作中要驱动的字线的单位确定为与冗余修复行单元相同的冗余修复行单元，该冗余修复行单元设置与所决定的刷新利用相对应的输入刷新利用地址的较低行地址 行驱动单位到不关心状态; 并且根据组合的刷新利用地址在内部生成不关心刷新利用地址的较低行地址来驱动字线。

    Memory device scrambling address
    19.
    发明授权
    Memory device scrambling address 有权

    公开(公告)号：US10957380B2

    公开(公告)日：2021-03-23

    申请号：US16369034

    申请日：2019-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-sung Shin ,  Dae-Jeong Kim ,  Ik-Joon Choi

    IPC: G11C11/40 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/406 ,  G06F3/06 ,  G11C17/18 ,  G11C17/16

    Abstract: According to an exemplary embodiment, a memory device may include a memory cell array that includes memory cells connected to word lines arranged in sequential order depending on a sequential change of a row address, a row decoder that, for each row address input to the row decoder, scrambles a first bit of the row address and a second bit of the row address depending on a selection signal, thereby forming a scrambled row address, decodes the scrambled row address, and selects a word line from the word lines based on the scrambled row address, and an anti-fuse array that includes an anti-fuse in which a logical value of the selection signal is programmed. A first word line and a second word line of the word lines may be adjacent to each other, and a difference between a first value of the row address corresponding to the first word line and a second value of the row address corresponding to the second word line may be a value corresponding to the first bit.

    MEMORY MODULE AND MEMORY SYSTEM INCLUDING MEMORY MODULE
    20.
    发明申请
    MEMORY MODULE AND MEMORY SYSTEM INCLUDING MEMORY MODULE 审中-公开

    公开(公告)号：US20190310784A1

    公开(公告)日：2019-10-10

    申请号：US16205357

    申请日：2018-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Joon Kim ,  Dae-Jeong Kim ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

    IPC: G06F3/06

    Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

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