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    SOFTWARE STACK AND PROGRAMMING FOR DPU OPERATIONS
    11.
    发明申请
    SOFTWARE STACK AND PROGRAMMING FOR DPU OPERATIONS 审中-公开

    公开(公告)号：US20180121130A1

    公开(公告)日：2018-05-03

    申请号：US15426015

    申请日：2017-02-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Shaungchen LI ,  Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

    IPC: G06F3/06 ,  G11C11/4094

    CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0683 ,  G11C7/1006 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

    DATAFLOW ACCELERATOR ARCHITECTURE FOR GENERAL MATRIX-MATRIX MULTIPLICATION AND TENSOR COMPUTATION IN DEEP LEARNING
    16.
    发明申请
    DATAFLOW ACCELERATOR ARCHITECTURE FOR GENERAL MATRIX-MATRIX MULTIPLICATION AND TENSOR COMPUTATION IN DEEP LEARNING 有权

    公开(公告)号：US20210374210A1

    公开(公告)日：2021-12-02

    申请号：US17374988

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Peng GU ,  Krishna MALLADI ,  Hongzhong ZHENG ,  Dimin NIU

    IPC: G06F17/16 ,  G06F12/0877 ,  G06F12/0802 ,  G06N3/063 ,  G06N3/00 ,  G06N3/04

    Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

    BANDWIDTH BOOSTED STACKED MEMORY
    17.
    发明申请
    BANDWIDTH BOOSTED STACKED MEMORY 有权

    公开(公告)号：US20210141735A1

    公开(公告)日：2021-05-13

    申请号：US17156362

    申请日：2021-01-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Krishna T. MALLADI ,  Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG

    IPC: G06F12/0879 ,  G11C11/417

    Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY
    18.
    发明申请
    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY 审中-公开

    公开(公告)号：US20200218447A1

    公开(公告)日：2020-07-09

    申请号：US16819032

    申请日：2020-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

    IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    MEMORY MODULE, OPERATION METHOD THEROF, AND OPERATION METHOD OF HOST
    19.
    发明申请
    MEMORY MODULE, OPERATION METHOD THEROF, AND OPERATION METHOD OF HOST 审中-公开

    公开(公告)号：US20190236030A1

    公开(公告)日：2019-08-01

    申请号：US16103058

    申请日：2018-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-Young LIM ,  Dimin NIU ,  Jae-Gon LEE

    IPC: G06F12/14 ,  G06F3/06 ,  G06F21/79

    CPC classification number: G06F12/1433 ,  G06F3/0622 ,  G06F3/0679 ,  G06F21/79

    Abstract: A memory module includes a random access memory (RAM) device that includes a first storage region and a second storage region, a nonvolatile memory device, and a controller that controls the RAM device or the nonvolatile memory device under control of a host. The controller includes a data buffer that temporarily stores first data received from the host, and a buffer returning unit that transmits first release information to the host when the first data are moved from the data buffer to the first storage region or the second storage region of the RAM device and transmits second release information to the host when the first data are moved from the second storage region to the nonvolatile memory device.

    SMART IN-MODULE REFRESH FOR DRAM
    20.
    发明申请
    SMART IN-MODULE REFRESH FOR DRAM 有权
    用于DRAM的SMART IN-MODULE刷新

    公开(公告)号：US20160307619A1

    公开(公告)日：2016-10-20

    申请号：US14850938

    申请日：2015-09-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Krishna MALLADI ,  Dimin NIU ,  Hongzhong ZHENG

    IPC: G11C11/406 ,  G11C11/4076

    CPC classification number: G11C11/40615 ,  G11C5/04 ,  G11C5/14 ,  G11C11/40618 ,  G11C11/4076

    Abstract: A dynamic Random Access Memory (DRAM) module (105) is disclosed. The DRAM module (105) can includes a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data and a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4). The DRAM module (105) can also include a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

    Abstract translation: 公开了一种动态随机存取存储器（DRAM）模块（105）。 DRAM模块（105）可以包括用于存储数据的多个存储体（205-1,205-2,205-3,205-4）和可用于刷新多个存储数据中的一个的刷新引擎（115） 银行（205-1,205-2,205-3,205-4）。 DRAM模块（105）还可以包括智能刷新组件（305），该智能刷新组件可以通过使用每次刷新无序刷新哪个存储体来刷新刷新引擎（115）。 在刷新时，智能刷新组件（305）可以使用逻辑（415）来识别事务队列（430）中的待处理事务中的最远存储体。

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