公开(公告)号：US11004985B2

公开(公告)日：2021-05-11

申请号：US16793162

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/092

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US10693017B2

公开(公告)日：2020-06-23

申请号：US16435263

申请日：2019-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L27/092 ,  B82Y10/00 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US10008600B2

公开(公告)日：2018-06-26

申请号：US15685459

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeong Chan Lee ,  Cho Eun Lee ,  Su Jin Jung ,  Gyeom Kim ,  Ji Eon Yoon

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7834

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

公开(公告)号：US10008575B2

公开(公告)日：2018-06-26

申请号：US15298746

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Chan Suh ,  Yong Suk Tak ,  Gi Gwan Park ,  Mi Seon Park ,  Moon Seung Yang ,  Seung Hun Lee ,  Poren Tang

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L29/42376 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/7831 ,  H01L29/78696

Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.

公开(公告)号：US09530870B2

公开(公告)日：2016-12-27

申请号：US14805876

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieon Yoon ,  Seokhoon Kim ,  Gyeom Kim ,  Nam-Kyu Kim ,  JinBum Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/04 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., and any other direction) of the semiconductor substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极图案，将非晶化元件注入到半导体衬底中以在栅极图案的一侧形成非晶部分，去除非晶部分以形成凹陷区域，并且形成源极/漏极图案 凹陷区域。 当形成凹陷区域时，非晶部分的蚀刻速率在半导体衬底的两个不同方向（例如，<111>和任何其它方向）上基本相同。

公开(公告)号：US12142671B2

公开(公告)日：2024-11-12

申请号：US17514008

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US11682735B2

公开(公告)日：2023-06-20

申请号：US17231120

申请日：2021-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/068 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684 ,  Y10S977/762 ,  Y10S977/765 ,  Y10S977/938

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US10692993B2

公开(公告)日：2020-06-23

申请号：US15956166

申请日：2018-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Chan Suh ,  Sangmoon Lee ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.

公开(公告)号：US10319863B2

公开(公告)日：2019-06-11

申请号：US15373065

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hun Lee ,  Dong Woo Kim ,  Dong Chan Suh ,  Sun Jung Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/08

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

公开(公告)号：US09502532B2

公开(公告)日：2016-11-22

申请号：US14707144

申请日：2015-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Bum Park ,  Dong Chan Suh ,  Kwan Heum Lee

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a method of manufacturing a semiconductor device including: forming a gate electrode structure on an active region of a semiconductor substrate; forming recesses in regions positioned on both sides of the gate electrode structure on the active region; performing a pre-treatment on the recesses using an inert gas plasma; growing epitaxial layers for a source and a drain on the pre-treated recesses; and forming a source electrode structure and a drain electrode structure in the epitaxial layers for the source and the drain, respectively. Also provided is a method in which, after an etching process for forming recesses and/or after an etching process for forming a contact hole, an etched surface may be treated with an inert gas plasma before growing an epitaxial layer. Thus, one or two types of plasma treatment may be employed in the method.

Abstract translation: 提供一种制造半导体器件的方法，包括：在半导体衬底的有源区上形成栅电极结构; 在所述有源区上形成位于所述栅电极结构两侧的区域中的凹槽; 使用惰性气体等离子体对凹部进行预处理; 在预处理的凹槽上生长用于源极和漏极的外延层; 以及在源极和漏极的外延层中分别形成源极结构和漏极结构。 还提供了一种方法，其中在用于形成凹陷的蚀刻工艺和/或用于形成接触孔的蚀刻工艺之后，可以在生长外延层之前用惰性气体等离子体处理蚀刻表面。 因此，在该方法中可以采用一种或两种类型的等离子体处理。