公开(公告)号：US20220310852A1

公开(公告)日：2022-09-29

申请号：US17840737

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Woo Seok PARK ,  Dong Chan SUH ,  Seung Min SONG ,  Geum Jong BAE ,  Dong Il BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

公开(公告)号：US20220085161A1

公开(公告)日：2022-03-17

申请号：US17229045

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo NOH ,  Myung Gil KANG ,  Tae Young KIM ,  Geum Jong BAE ,  Keun Hwi CHO

IPC: H01L29/06

Abstract: A semiconductor device includes a substrate, first to sixth nanowires extending in a first direction and spaced apart from each other, first to third gate electrodes extending in a second direction and respectively on first to third regions of the substrate, a first interface layer of a first thickness between the first gate electrode and the second nanowire, a second interface layer of a second thickness between the third gate electrode and the sixth nanowire. The first to third gate electrodes respectively may surround the first and second nanowires, third and fourth nanowires, and fifth and sixth nanowires. A first internal spacer may be on a side wall of at least one of the first to third gate electrodes. In the first direction, a first length of the first nanowire may be smaller than a second length of the third nanowire.

公开(公告)号：US20210358923A1

公开(公告)日：2021-11-18

申请号：US17387192

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil YANG ,  Sun Wook KIM ,  Jun Beom PARK ,  Tae Young KIM ,  Geum Jong BAE

IPC: H01L27/11 ,  H01L23/528

Abstract: A semiconductor device includes first and second fin type patterns, first and second gate patterns intersecting the first and second fin type patterns, third and fourth gate patterns intersecting the first fin type pattern between the first and the second gate patterns, a fifth gate pattern intersecting the second fin type pattern, a sixth gate pattern intersecting the second fin type pattern, first to third semiconductor patterns disposed among the first, the third, the fourth and the second gate patterns, and fourth to sixth semiconductor patterns disposed among the first, the fifth, the sixth and the second gate patterns. The first semiconductor pattern to the fourth semiconductor pattern and the sixth semiconductor pattern are electrically connected to a wiring structure, and the fifth semiconductor pattern is not connected to the wiring structure.

公开(公告)号：US20200013777A1

公开(公告)日：2020-01-09

申请号：US16574887

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min KIM ,  Dong Won KIM ,  Geum Jong BAE

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.

公开(公告)号：US20190088789A1

公开(公告)日：2019-03-21

申请号：US16161765

申请日：2018-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Woo Seok PARK ,  Geum Jong BAE ,  Dong Il BAE ,  Jung Gil YANG

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423

Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

公开(公告)号：US20170256608A1

公开(公告)日：2017-09-07

申请号：US15444550

申请日：2017-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Dae SUK ,  Seung Min SONG ,  Geum Jong BAE

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/786

Abstract: A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.

公开(公告)号：US20170250291A1

公开(公告)日：2017-08-31

申请号：US15222276

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ho LEE ,  Ho Jun KIM ,  Sung Dae SUK ,  Geum Jong BAE

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.