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公开(公告)号：US20250104764A1
公开(公告)日：2025-03-27
申请号：US18972079
申请日：2024-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungyeon Kim , Jooyong Park , Hongsoo Jeon
IPC: G11C11/4099 , G11C11/408 , G11C11/4097
Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.
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公开(公告)号：US12107061B2
公开(公告)日：2024-10-01
申请号：US17513132
申请日：2021-10-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Homoon Shin , Jooyong Park , Hongsoo Jeon , Pansuk Kwak
IPC: H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
CPC classification number: H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
Abstract: An integrated circuit device includes; a peripheral circuit structure including a peripheral circuit, a first insulating layer covering the peripheral circuit, extension lines in the first insulating layer, and a first bonding pad in the first insulating layer, and a cell array structure including a conductive plate, a memory cell array below the conductive plate, a second insulating layer covering the memory cell array, a second bonding pad in the second insulating layer, a conductive via on the conductive plate, and a line connected to the conductive via. The first bonding pad contacts the second bonding pad, and the integrated circuit device further includes contact plugs electrically connecting the line to the extension lines.
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公开(公告)号：US11942154B2
公开(公告)日：2024-03-26
申请号：US17825764
申请日：2022-05-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hongsoo Jeon , Bongsoon Lim , Sangwan Nam
CPC classification number: G11C16/0433 , G11C5/063 , G11C16/08 , G11C16/20
Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.
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公开(公告)号：US20240071517A1
公开(公告)日：2024-02-29
申请号：US18504093
申请日：2023-11-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungyeon Kim , Daeseok Byeon , Pansuk Kwak , Hongsoo Jeon
Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
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公开(公告)号：US11837293B2
公开(公告)日：2023-12-05
申请号：US17898885
申请日：2022-08-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungyeon Kim , Daeseok Byeon , Pansuk Kwak , Hongsoo Jeon
Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.
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Patent Agency Ranking
公开(公告)号：US11515325B2
公开(公告)日：2022-11-29
申请号：US17025479
申请日：2020-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongsoon Lim , Sang-Wan Nam , Sang-Won Park , Sang-Won Shim , Hongsoo Jeon , Yonghyuk Choi
IPC: H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L23/522 , G11C7/18 , H01L27/11556 , H01L27/11526 , G11C8/14 , H01L27/11519
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
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公开(公告)号：US12224277B2
公开(公告)日：2025-02-11
申请号：US18149206
申请日：2023-01-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk Choi , Bongsoon Lim , Hongsoo Jeon , Jaeduk Yu
IPC: H01L23/528 , G11C16/04 , G11C16/08 , H01L23/00 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/112
Abstract: A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.
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公开(公告)号：US11854982B2
公开(公告)日：2023-12-26
申请号：US17982255
申请日：2022-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongsoon Lim , Sang-Wan Nam , Sang-Won Park , Sang-Won Shim , Hongsoo Jeon , Yonghyuk Choi
IPC: H01L23/535 , H10B43/27 , H10B43/40
CPC classification number: H01L23/535 , H10B43/40
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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公开(公告)号：US11763879B2
公开(公告)日：2023-09-19
申请号：US17322065
申请日：2021-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoonjee Kim , Seungyeon Kim , Sangwan Nam , Hongsoo Jeon , Jiho Cho
IPC: G11C11/4097 , G11C5/06 , G11C11/4093 , G11C11/408 , G11C11/4099
CPC classification number: G11C11/4097 , G11C5/06 , G11C11/4085 , G11C11/4087 , G11C11/4093 , G11C11/4099
Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.
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公开(公告)号：US20230162791A1
公开(公告)日：2023-05-25
申请号：US17825764
申请日：2022-05-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hongsoo Jeon , Bongsoon Lim , Sangwan Nam
CPC classification number: G11C16/0433 , G11C16/08 , G11C16/20 , G11C5/063
Abstract: A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.
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