公开(公告)号：US10796767B2

公开(公告)日：2020-10-06

申请号：US16199098

申请日：2018-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Minsu Kim ,  Hyun-Wook Park ,  Bongsoon Lim

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/24 ,  G11C16/04

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes first and second cell strings respectively connected to first and second bit lines. The page buffer circuit is configured to apply an erase voltage to the first bit line and to allow the second bit line to be in a floating state, when an erase operation is performed on memory cells of the first and second cell strings.

公开(公告)号：US09767912B2

公开(公告)日：2017-09-19

申请号：US15172301

申请日：2016-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Wook Park ,  Kitae Park ,  Jaeyong Jeong

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C11/56 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445

Abstract: An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate based on a first operation mode to operate based on a second operation mode; and performing a change erase operation on the memory cells for which an operation mode is changed on the basis of a change erase condition when the operation mode is changed. When memory cells operate in the first operation mode, a normal erase operation is performed based on a first erase condition, and when memory cells operate in the second operation mode, a normal erase operation is performed based on a second erase condition. The change erase condition is different from at least one of the first and second erase conditions.

公开(公告)号：US09466386B2

公开(公告)日：2016-10-11

申请号：US14336343

申请日：2014-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Wook Park ,  Jung-Soo Kim ,  Jaeyong Jeong ,  Kitae Park ,  Youngsun Song

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/22 ,  G11C16/10

CPC classification number: G11C16/225 ,  G11C16/0483 ,  G11C16/10

Abstract: A method of programming a storage device comprises determining whether at least one open page exists in a memory block of a nonvolatile memory device, and as a consequence of determining that at least one open page exists in the memory block, closing the at least one open page through a dummy pattern program operation, and thereafter performing a continuous writing operation on the memory block.

Abstract translation: 一种对存储设备进行编程的方法包括确定至少一个开放页面是否存在于非易失性存储器件的存储器块中，并且作为确定存储器块中存在至少一个打开页面的结果，关闭至少一个打开的 通过虚拟图案编程操作，然后对存储块进行连续写入操作。

公开(公告)号：US11688478B2

公开(公告)日：2023-06-27

申请号：US17694229

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Jin Song ,  Hyun-Wook Park ,  Bong-Soon Lim ,  Do-Bin Kim

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/14 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

公开(公告)号：US11227660B2

公开(公告)日：2022-01-18

申请号：US17016572

申请日：2020-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyeon Yu ,  Minsu Kim ,  Hyun-Wook Park ,  Bongsoon Lim

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C7/10 ,  G11C16/04 ,  G11C16/30

Abstract: A memory device includes a cell array and a page buffer circuit. The cell array includes a first to fourth cell strings respectively connected to a first to fourth bit lines. The page buffer circuit is configured to apply an erase voltage to the first and third bit lines based on a first control signal during an erase operation for memory cells of the first to fourth cell strings. The page buffer circuit is configured to place the second and fourth bit lines in a floating state based on a second control signal during the erase operation.

公开(公告)号：US10268575B2

公开(公告)日：2019-04-23

申请号：US15813903

申请日：2017-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Yoon Park ,  Hyun-Wook Park

IPC: G06F12/02 ,  H01L27/115 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

Abstract: A nonvolatile memory device includes control logic and a memory cell array. The memory cell array includes a first plane and a second plane. The control logic is configured to perform a first sub-operation on the first plane, to perform a second sub-operation on the second plane, to delay the second sub-operation as much as a reference time so that a partial section of the first sub-operation does not overlap the second sub-operation, and to variably control the reference time.

公开(公告)号：US09824761B2

公开(公告)日：2017-11-21

申请号：US15138302

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DongHun Kwak ,  Dongkyo Shim ,  Kitae Park ,  Hyun-Wook Park

IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495

Abstract: A programming method of a nonvolatile memory device including; programming data in memory cells connected to a word line by performing a coarse program operation; and programming the data in the memory cells by performing a fine program operation, wherein the number of program states in the coarse program operation is changed according to a program/erase (P/E) cycle number.

公开(公告)号：US09336866B2

公开(公告)日：2016-05-10

申请号：US14188889

申请日：2014-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DongHun Kwak ,  Dongkyo Shim ,  Kitae Park ,  Hyun-Wook Park

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495

Abstract: A write method of a storage device includes determining whether to perform a coarse program operation based on information about memory cells of a memory device, in response to a determination that the coarse program operation is to be performed, programming data in the memory device by performing the coarse program operation and a fine program operation, and in response to a determination that the coarse program operation is not to be performed, programming data in the memory device by performing the fine program operation.

Abstract translation: 存储装置的写入方法包括响应于要执行粗略编程操作的确定，基于关于存储器件的存储器单元的信息来确定是否执行粗略编程操作，通过执行存储器件中的程序数据 粗程序操作和精细程序操作，并且响应于不执行粗程序操作的确定，通过执行精细程序操作来在存储器件中编程数据。

公开(公告)号：US08942296B2

公开(公告)日：2015-01-27

申请号：US14164875

申请日：2014-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yung-Iyul Lee ,  Hyun-Wook Park

IPC: H04N7/12 ,  H04N19/189 ,  H04N19/80 ,  H04N19/527 ,  H04N19/117 ,  H04N19/14 ,  H04N19/44 ,  H04N19/172 ,  H04N19/86 ,  H04N19/159 ,  H04N19/61 ,  H04N19/90 ,  H04N19/157 ,  H04N19/48 ,  G06T5/00 ,  G06T5/20

CPC classification number: H04N19/00 ,  G06T5/00 ,  G06T5/002 ,  G06T5/20 ,  G06T2207/20008 ,  H04N19/117 ,  H04N19/124 ,  H04N19/127 ,  H04N19/136 ,  H04N19/14 ,  H04N19/157 ,  H04N19/159 ,  H04N19/172 ,  H04N19/182 ,  H04N19/189 ,  H04N19/44 ,  H04N19/48 ,  H04N19/527 ,  H04N19/60 ,  H04N19/61 ,  H04N19/80 ,  H04N19/86 ,  H04N19/90

Abstract: A signal adaptive filtering method for reducing blocking effect and ringing noise, a signal adaptive filter, and a computer readable medium. The signal adaptive filtering method capable of reducing blocking effect and ringing noise of image data when a frame is composed of blocks of a predetermined size includes the steps of: (a) generating blocking information for reducing the blocking effect and ringing information for reducing the ringing noise, from coefficients of predetermined pixels of the upper and left boundary regions of the data block when a frame obtained by deconstructing a bitstream image data for inverse quantization is an intraframe; and (b) adaptively filtering the image data passed through inverse quantization and inverse discrete cosine transform according to the generated blocking information and ringing information. Therefore, the blocking effect and ringing noise can be eliminated from the image restored from the block-based image, thereby enhancing the image restored from compression.

公开(公告)号：US08867275B2

公开(公告)日：2014-10-21

申请号：US13625114

申请日：2012-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Hwan Shin ,  Kitae Park ,  Hyun-Wook Park ,  Jun-Hee Lee

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C16/06

Abstract: Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region.

Abstract translation: 公开了一种闪速存储器件和编程方法，包括： 接收缓冲器数据，并在缓冲器数据的高速模式和可靠性模式之间确定，并且在确定将缓冲器数据存储在第一缓冲区域中的可靠性模式时，并且在确定将第二缓冲器数据存储在第二缓冲器数据中的高速模式 缓冲区。 闪速存储器的存储单元阵列包括分为第一缓冲区域和第二缓冲区域的主区域和单独指定的缓冲区域。