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公开(公告)号：US12072637B2
公开(公告)日：2024-08-27
申请号：US17971297
申请日：2022-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon Lee , Changyoung Jeong , Byunggook Kim , Maenghyo Cho , Muyoung Kim , Junghwan Moon , Sungwoo Park , Hyungwoo Lee , Joonmyung Choi
IPC: G03F7/00 , G05B19/4097 , H01L21/027
CPC classification number: G03F7/705 , G05B19/4097 , H01L21/0273 , G05B2219/45028
Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.
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公开(公告)号：US20230047588A1
公开(公告)日：2023-02-16
申请号：US17971297
申请日：2022-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon Lee , Changyoung Jeong , Byunggook Kim , Maenghyo Cho , Muyoung Kim , Junghwan Moon , Sungwoo Park , Hyungwoo Lee , Joonmyung Choi
IPC: G03F7/20 , H01L21/027 , G05B19/4097
Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.
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公开(公告)号：US11581042B2
公开(公告)日：2023-02-14
申请号：US17181259
申请日：2021-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo Lee , Sangjoon Kim , Seungchul Jung , Yongmin Ju
Abstract: Provided are processing and an electronic device including the same. The processing apparatus includes a bit cell line comprising bit cells connected in series, a mirror circuit unit configured to generate a mirror current by replicating a current flowing through the bit cell line at a ratio, a charge charging unit configured to charge a voltage corresponding to the mirror current as the mirror current replicated by the mirror circuit unit is applied, and a voltage measuring unit configured to output a value corresponding to a multiply-accumulate (MAC) operation of weights and inputs applied to the bit cell line, based on the voltage charged by the charge charging unit.
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公开(公告)号：US11493850B2
公开(公告)日：2022-11-08
申请号：US16593149
申请日：2019-10-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon Lee , Changyoung Jeong , Byunggook Kim , Maenghyo Cho , Muyoung Kim , Junghwan Moon , Sungwoo Park , Hyungwoo Lee , Joonmyung Choi
IPC: G03F7/20 , H01L21/027 , G05B19/4097
Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.
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公开(公告)号：US11447910B2
公开(公告)日：2022-09-20
申请号：US17011896
申请日：2020-09-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jungchul Choi , Sungmo Lee , Jeonghoon Kang , Hyungwoo Lee
IPC: F26B13/10 , D06F58/38 , D06F58/46 , D06F103/04 , D06F103/10 , D06F105/32 , D06F105/46 , D06F105/56
Abstract: A controlling method for a dryer is provided. The controlling method includes the steps of rotating a drum in a first direction and a second direction which is an opposite direction to the first direction by a motor, measuring the load of the motor and identifying the weight of drying materials based on the lower motor load among the load of the motor measured during rotation in the first direction and the load of the motor measured during rotation in the second direction.
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Patent Agency Ranking
公开(公告)号：US11992683B2
公开(公告)日：2024-05-28
申请号：US18118376
申请日：2023-03-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo Lee , Sang Joon Kim , Jongpal Kim
IPC: A61N1/24 , A61B5/0536 , A61B5/24 , A61N1/36
CPC classification number: A61N1/36125 , A61B5/0536 , A61B5/24
Abstract: Aspects of the subject disclosure may include, for example, a method and apparatus for measuring a bioimpedance and performing an electrical stimulation, the method including generating a first current corresponding to a first high-frequency, generating a second current corresponding to a second high-frequency, generating a low-frequency current based on a beat phenomenon of the first current and the second current, and calculating an impedance of a target part based on a voltage induced to the target part by a high-frequency current corresponding to at least one of the first current and the second current and the low-frequency current.
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公开(公告)号：US11962960B2
公开(公告)日：2024-04-16
申请号：US17888889
申请日：2022-08-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungwoo Lee , Jongchun Wee , Byounguk Yoon
CPC classification number: H04R1/023 , H04R1/025 , H04R1/04 , H04R1/086 , H04R3/00 , H04R2201/029 , H04R2400/11 , H04R2499/11
Abstract: A sound component assembly includes: a sealing portion provided in a sound passage connected to a sound hole of an electronic device to surround a portion of the sound passage and contact at least a portion of a printed circuit board (PCB) having a sound module mounted thereon; and a cover portion disposed to face the PCB outside the sealing portion, wherein the sealing portion may include a first material, the cover portion may include a second material, and the second material may have a greater hardness than a hardness of the first material.
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公开(公告)号：US11756610B2
公开(公告)日：2023-09-12
申请号：US17974852
申请日：2022-10-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongmin Ju , Sangjoon Kim , Hyungwoo Lee , Seungchul Jung
IPC: G11C7/12 , G11C11/54 , G11C11/4074 , G11C11/4076 , G11C11/4091 , G11C7/10 , G11C27/02
CPC classification number: G11C11/54 , G11C11/4074 , G11C11/4076 , G11C11/4091 , G11C7/1006 , G11C27/02
Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.
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公开(公告)号：US11738191B2
公开(公告)日：2023-08-29
申请号：US16189177
申请日：2018-11-13
Inventor： Hyungwoo Lee , Duk Lyul Na , Dae Won Seo , Young Min Shon , Jin San Lee , Woo Ram Jung , Sang Joon Kim , Joonseong Kang , Wonseok Lee
IPC: A61N1/05 , G06F3/01 , A61B5/00 , A61N1/36 , A61N1/378 , H02J50/10 , A61N1/372 , A61B5/053 , A61B5/01 , A61B5/30 , A61B5/291 , A61B5/316 , A61B5/375
CPC classification number: A61N1/0529 , A61B5/0031 , A61B5/4064 , A61B5/4836 , A61N1/36135 , G06F3/015 , A61B5/0006 , A61B5/0008 , A61B5/01 , A61B5/053 , A61B5/291 , A61B5/30 , A61B5/316 , A61B5/375 , A61B2560/0219 , A61N1/36064 , A61N1/36103 , A61N1/3787 , A61N1/37247 , A61N1/37264 , H02J50/10
Abstract: Disclosed are a medical device apparatus, system, and method. A method includes receiving biometric information, by an external device external to a body of a user, of the user from an internal device within the body of the user, and wirelessly transmitting stimulus information configured to specify a stimulus based on the biometric information, and power to the internal device configured to drive the internal device and to apply the stimulus in response to the transmitted stimulus information. A method also includes wirelessly transmitting, from an internal device in a body of a user, biometric information of the user to an external device located outside the body of the user, and wirelessly receiving from the external device stimulus information configured to specify a stimulus, and power configured to drive the internal device and to apply the stimulus to the user in response to the received stimulus information.
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公开(公告)号：US11587616B2
公开(公告)日：2023-02-21
申请号：US17141474
申请日：2021-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungwoo Lee , Sangjoon Kim , Yongmin Ju
Abstract: An apparatus for performing in-memory processing includes a memory cell array of memory cells configured to output a current sum of a column current flowing in respective column lines of the memory cell array based on an input signal applied to row lines of the memory cells, a sampling circuit, comprising a capacitor connected to each of the column lines, configured to be charged by a sampling voltage of a corresponding current sum of the column lines, and a processing circuit configured to compare a reference voltage and a currently charged voltage in the capacitor in response to a trigger pulse generated at a timing corresponding to a quantization level, among quantization levels, time-sectioned based on a charge time of the capacitor, and determine the quantization level corresponding to the sampling voltage by performing time-digital conversion when the currently charged voltage reaches the reference voltage.
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