公开(公告)号：US09318482B2

公开(公告)日：2016-04-19

申请号：US14677289

申请日：2015-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo

IPC: H01L23/58 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/866

CPC classification number: H01L29/0692 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/861

Abstract: Provided are an electrostatic discharge (ESD) protection device having a high-resistance region and a method of forming the same. The device includes a well on a substrate. A first impurity region is formed on the well and connected to an input/output pad. A second impurity region is formed on the well, spaced apart from the first impurity region, and connected to a ground (Vss). A third impurity region is formed on the well, spaced apart from the first impurity region, and connected to the ground (Vss). An isolation layer is formed between the first impurity region and the second impurity region. A high-resistance region, which directly contacts the first impurity region and the well and has a resistance higher than the first impurity region, is formed between the first impurity region and the isolation layer. The well and the third impurity region include first conductive type impurities. The first impurity region and the second impurity region include second conductive type impurities different from the first conductive type impurities.

Abstract translation: 提供了具有高电阻区域的静电放电（ESD）保护装置及其形成方法。 该器件在衬底上包括阱。 第一杂质区形成在阱上并连接到输入/输出焊盘。 在阱上形成第二杂质区，与第一杂质区间隔开，并连接到地（Vss）。 在阱上形成第三杂质区，与第一杂质区间隔开，并连接到地（Vss）。 在第一杂质区和第二杂质区之间形成隔离层。 在第一杂质区域和隔离层之间形成有与第一杂质区域和阱直接接触并且具有高于第一杂质区域的电阻的高电阻区域。 阱和第三杂质区包括第一导电型杂质。 第一杂质区和第二杂质区包括与第一导电型杂质不同的第二导电型杂质。

公开(公告)号：US20150115375A1

公开(公告)日：2015-04-30

申请号：US14503811

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/45 ,  H01L21/321 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/517 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed on the lower gate electrode and has a width that gradually increases from a bottom portion toward a top portion thereof. The width of the bottom portion of the upper gate electrode is smaller than a width of a top surface of the lower gate electrode. The first inner spacer surrounds a sidewall of the upper gate electrode.

Abstract translation: 半导体器件包括栅极绝缘层图案，下部栅极电极，上部栅极电极和第一内部间隔物。 栅极绝缘层图案形成在基板上。 下栅电极形成在栅绝缘层图案上。 上栅电极形成在下栅电极上，并且具有从底部朝向其顶部逐渐增加的宽度。 上栅电极的底部的宽度小于下栅电极的顶表面的宽度。 第一内部间隔件围绕上部栅电极的侧壁。

公开(公告)号：US09935167B2

公开(公告)日：2018-04-03

申请号：US15268833

申请日：2016-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hyun Noh ,  Su-Tae Kim ,  Jae-Hyun Yoo ,  Byeong-Ryeol Lee ,  Jong-Sung Jeon

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/063 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

公开(公告)号：US09893053B2

公开(公告)日：2018-02-13

申请号：US14697707

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Kee-Moon Chun

IPC: H02H9/00 ,  H01L27/02 ,  H01L23/535 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L27/0274 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including an electrostatic discharge (ESD) protection circuit includes an input port, a logic circuit receiving an input signal applied to the input port and generating an output signal based on the input signal, and an ESD protection circuit adjusting a level of the input signal when the level of the input signal exceeds a predetermined range. The ESD protection circuit includes a first fin and a second fin arranged on a semiconductor substrate in parallel, and a gate electrode formed in a direction crossing the first fin and the second fin, each of the first fin and the second fin includes a source region, a drain region, and a channel region disposed between the source region and the drain region, the channel region is disposed under the gate electrode, a source region of the first fin and a drain region of the second fin are disposed at a first side of the gate electrode, and a drain region of the first fin and a source region of the second fin are disposed at a second side of the gate electrode.

公开(公告)号：US09679886B2

公开(公告)日：2017-06-13

申请号：US14509365

申请日：2014-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Jin-Tae Kim ,  Jong-Sung Jeon

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0285 ,  H01L27/0288 ,  H01L27/0629

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.

公开(公告)号：US20160064375A1

公开(公告)日：2016-03-03

申请号：US14677289

申请日：2015-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo

IPC: H01L27/02 ,  H01L29/866 ,  H01L29/36 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/0692 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/861

Abstract: Provided are an electrostatic discharge (ESD) protection device having a high-resistance region and a method of forming the same. The device includes a well on a substrate. A first impurity region is formed on the well and connected to an input/output pad. A second impurity region is formed on the well, spaced apart from the first impurity region, and connected to a ground (Vss). A third impurity region is formed on the well, spaced apart from the first impurity region, and connected to the ground (Vss). An isolation layer is formed between the first impurity region and the second impurity region. A high-resistance region, which directly contacts the first impurity region and the well and has a resistance higher than the first impurity region, is formed between the first impurity region and the isolation layer. The well and the third impurity region include first conductive type impurities. The first impurity region and the second impurity region include second conductive type impurities different from the first conductive type impurities.

Abstract translation: 提供了具有高电阻区域的静电放电（ESD）保护装置及其形成方法。 该器件在衬底上包括阱。 第一杂质区形成在阱上并连接到输入/输出焊盘。 在阱上形成第二杂质区，与第一杂质区间隔开，并连接到地（Vss）。 在阱上形成第三杂质区，与第一杂质区间隔开，并连接到地（Vss）。 在第一杂质区和第二杂质区之间形成隔离层。 在第一杂质区域和隔离层之间形成有与第一杂质区域和阱直接接触并且具有高于第一杂质区域的电阻的高电阻区域。 阱和第三杂质区包括第一导电型杂质。 第一杂质区和第二杂质区包括与第一导电型杂质不同的第二导电型杂质。

公开(公告)号：US10186505B2

公开(公告)日：2019-01-22

申请号：US15603969

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Jin-Tae Kim ,  Jong-Sung Jeon

IPC: H01L27/02 ,  H01L27/06

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.

公开(公告)号：US20160372456A1

公开(公告)日：2016-12-22

申请号：US15155361

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Jong-Sung JEON

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0642 ,  H01L29/0684

Abstract: A semiconductor device includes a first well in a substrate, a gate structure on the first well, a second well below the gate structure in the first well, a third well in a first side of the gate structure and in the first well to be adjacent to the second well, the third well having a conductivity type different from that of the second well, a fourth well overlapped with the third well, a fifth well in a second side of the gate structure and in the second well, a sixth well below the gate structure and in the second well, the sixth well being adjacent to the fifth well and having an impurity concentration higher than the impurity concentration of the second well, and a first device isolation layer overlapped with the second well and disposed farther away from the gate structure than the fifth well.

Abstract translation: 半导体器件包括衬底中的第一阱，第一阱上的栅极结构，第一阱中的栅极结构下面的第二阱，栅极结构的第一侧中的第三阱以及与第一阱相邻的第一阱 到第二阱，第三阱具有不同于第二阱的导电类型，第四阱与第三阱重叠，第五阱在栅极结构的第二侧中，在第二阱中，第六阱在下面 所述栅极结构，并且在所述第二阱中，所述第六阱与所述第五阱相邻，并且具有高于所述第二阱的杂质浓度的杂质浓度，以及与所述第二阱重叠并且远离所述第二阱的第二阱重叠的第一器件隔离层 门结构比第五井。

公开(公告)号：US09508820B2

公开(公告)日：2016-11-29

申请号：US14503811

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/517 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed on the lower gate electrode and has a width that gradually increases from a bottom portion toward a top portion thereof. The width of the bottom portion of the upper gate electrode is smaller than a width of a top surface of the lower gate electrode. The first inner spacer surrounds a sidewall of the upper gate electrode.

Abstract translation: 半导体器件包括栅极绝缘层图案，下部栅极电极，上部栅极电极和第一内部间隔物。 栅极绝缘层图案形成在基板上。 下栅电极形成在栅绝缘层图案上。 上栅电极形成在下栅电极上，并且具有从底部朝向其顶部逐渐增加的宽度。 上栅电极的底部的宽度小于下栅电极的顶表面的宽度。 第一内部间隔件围绕上部栅电极的侧壁。

公开(公告)号：US20160035905A1

公开(公告)日：2016-02-04

申请号：US14714405

申请日：2015-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo

IPC: H01L29/866 ,  H01L29/06 ,  H01L29/36 ,  H01L27/02

CPC classification number: H01L29/866 ,  H01L27/0255 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66106

Abstract: Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well.

Abstract translation: 提供半导体器件。 半导体器件包括在衬底中形成的第一阱; 形成在第一井上的元件隔离层; 在所述元件隔离层的第一侧上的所述第一阱中形成的第二阱; 在第二井中形成的第三井，第三井具有比第二井更高的杂质浓度; 电连接到第三阱的第一电极; 第四阱，形成在元件隔离层的第二侧上的第一阱中; 在第四井中形成第五井，第五井具有与第四井不同的导电类型; 电连接到第五阱的第二电极; 第六井与第四井重叠，第六井具有比第四井更低的杂质浓度。