公开(公告)号：US20210028228A1

公开(公告)日：2021-01-28

申请号：US16794845

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Chul Lee ,  Eunsun Noh ,  Jeong-Heon Park ,  Ung Hwan Pi

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32

Abstract: A magnetic memory device includes a conductive line extending in a first direction, a bottom electrode provided on a portion of a bottom surface of the conductive line, a free layer and a pinned layer stacked on the conductive line, a spacer layer between the free layer and the pinned layer, and a top electrode provided on a portion of a top surface of the pinned layer. The conductive line, the free layer, the pinned layer and the spacer layer have side surfaces perpendicular to the first direction, and the side surfaces are aligned with each other.

公开(公告)号：US10804458B2

公开(公告)日：2020-10-13

申请号：US16242555

申请日：2019-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SAMSUNG ELECTRONICS, CO., LTD.

Inventor： Guohan Hu ,  Younghyun Kim ,  Chandrasekara Kothandaraman ,  Jeong-Heon Park

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a free magnetic layer formed on the tunnel barrier layer. A first boron-segregating layer is formed directly on the free magnetic layer. An anneal is performed to cause boron to leave the free magnetic layer at an interface with the first boron-segregating layer. A top electrode is formed over the memory stack.

公开(公告)号：US10777737B2

公开(公告)日：2020-09-15

申请号：US16540146

申请日：2019-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Shik Kim ,  Jeong-Heon Park ,  Gwan-Hyeob Koh

IPC: H01L29/82 ,  H01L43/00 ,  G11C11/00 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L29/417

Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

公开(公告)号：US20190115527A1

公开(公告)日：2019-04-18

申请号：US16107242

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Heon Park ,  Yong Sung Park ,  Joonmyoung Lee ,  Hyun Cho ,  Se Chung Oh

IPC: H01L43/12 ,  G11C11/16 ,  G11C11/15 ,  H01L43/02

Abstract: Provided are process control methods and process control systems. The method includes performing a deposition process on a lot defined by a group of a plurality of wafers, performing a measurement process on the lot to obtain a measured value with respect to at least one wafer among the plurality of wafers, producing a target value of a factor of a process condition in the deposition process by using a difference between the measured value and a reference value, and providing an input value of the factor with respect to a subsequent lot based on the target value. The operation of providing the input value of the factor includes obtaining a previous target value of the factor previously produced with respect to at least one previous lot, and providing a weighted average of the previous target value and the target value as the input value.

公开(公告)号：US10256399B2

公开(公告)日：2019-04-09

申请号：US15157834

申请日：2016-05-18

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

Inventor： Guohan Hu ,  Kwangseok Kim ,  Younghyun Kim ,  Jung-Hyuk Lee ,  Jeong-Heon Park

IPC: H01L43/12 ,  H01L43/10

Abstract: A method for manufacturing a semiconductor device includes forming a magnetic tunnel junction (MTJ) structure comprising a magnetic fixed layer, a non-magnetic barrier layer and a magnetic free layer, and forming a metal oxide cap layer on the MTJ structure, wherein forming the metal oxide cap layer comprises depositing a metal layer on the magnetic free layer, performing an oxidation of the deposited metal layer to form an oxidized metal layer, and depositing a metal oxide layer on the oxidized metal layer.

公开(公告)号：US20180358068A1

公开(公告)日：2018-12-13

申请号：US15802838

申请日：2017-11-03

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd.

Inventor： Guohan Hu ,  Jeong-Heon Park ,  Daniel C. Worledge

IPC: G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element that includes a reference layer, a tunnel barrier and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The reference layer has a fixed magnetization direction. The free layer includes a first region, a second region and a third region. The third region is formed from a third material that is configured to magnetically couple the first region and the second region. The first region is formed from a first material having a first predetermined magnetic moment, and the second region is formed from a second material having a second predetermined magnetic moment. The first predetermined magnetic moment is lower that the second predetermined magnetic moment.

公开(公告)号：US20230180625A1

公开(公告)日：2023-06-08

申请号：US17817441

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonmyoung Lee ,  Junghwan Park ,  Jeong-Heon Park ,  Kyungil Hong

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic memory device includes a first magnetic pattern and a second magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the first magnetic pattern and the second magnetic pattern, a lower electrode between the substrate and the first magnetic pattern, a blocking pattern between the lower electrode and the first magnetic pattern, a metal oxide pattern between the blocking pattern and the first magnetic pattern, and a buffer pattern between the metal oxide pattern and the first magnetic pattern. The lower electrode, the blocking pattern, the metal oxide pattern, and the buffer pattern include first, second, third, and fourth non-magnetic metals, respectively. The metal oxide pattern has an amorphous phase.

公开(公告)号：US11659770B2

公开(公告)日：2023-05-23

申请号：US17004637

申请日：2020-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Shik Kim ,  Jeong-Heon Park ,  Gwan-Hyeob Koh

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L29/417

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228 ,  H01L29/41791 ,  H01L43/02 ,  H01L43/08

Abstract: In a method of manufacturing an MRAM device, first and second lower electrodes may be formed on first and second regions, respectively, of a substrate. First and second MTJ structures having different switching current densities from each other may be formed on the first and second lower electrodes, respectively. First and second upper electrodes may be formed on the first and second MTJ structures, respectively.

公开(公告)号：US11535929B2

公开(公告)日：2022-12-27

申请号：US16898609

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Heon Park ,  Whankyun Kim ,  Sukhoon Kim ,  Junho Jeong

IPC: C23C14/46 ,  H01L21/687 ,  H01L21/67 ,  H01L21/677

Abstract: An ion beam deposition apparatus includes a substrate assembly to secure a substrate, a target assembly slanted with respect to the substrate assembly, the target assembly including a target with deposition materials, an ion gun to inject ion beams onto the target, such that ions of the deposition materials are discharged toward the substrate assembly to form a thin layer on the substrate, and a substrate heater to heat the substrate to a deposition temperature higher than a room temperature.

公开(公告)号：US10910552B2

公开(公告)日：2021-02-02

申请号：US16352957

申请日：2019-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonmyoung Lee ,  Yong Sung Park ,  Jeong-Heon Park ,  Hyun Cho ,  Ung Hwan Pi

IPC: H01L43/02 ,  H01L43/10 ,  H01L21/67 ,  G11C14/00 ,  H01L43/12 ,  H01L27/108 ,  H01L27/22 ,  H01L27/11 ,  G11C11/16

Abstract: A magnetic memory device, a method for manufacturing a magnetic memory device, and a substrate treating apparatus, the device including a substrate including a first memory region and a second memory region; a first magnetic tunnel junction pattern on the first memory region, the first magnetic tunnel junction pattern including a first free pattern and a first oxide pattern on the first free pattern; and a second magnetic tunnel junction pattern on the second memory region, the second magnetic tunnel junction pattern including a second free pattern and a second oxide pattern on the second free pattern, wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.