公开(公告)号：US20240332228A1

公开(公告)日：2024-10-03

申请号：US18535351

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon SHIN ,  Yeonjin LEE ,  Jongmin LEE ,  Jimin CHOI

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02206 ,  H01L2224/05016 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/16145

Abstract: A semiconductor device includes an insulating structure on a semiconductor substrate, lower conductive patterns in the insulating structure, upper conductive patterns on the insulating structure, conductive vias in the insulating structure and connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns, a protective layer covering the insulating structure and the upper conductive patterns, an etch stop layer covering the protective layer, a first passivation layer on portions of the etch stop layer between the upper conductive patterns, and an upper passivation layer on the first passivation layer.

公开(公告)号：US20240113077A1

公开(公告)日：2024-04-04

申请号：US18230768

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nara LEE ,  Yeonjin LEE ,  Jimin CHOI ,  Jongmin LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes a plurality of first semiconductor chips sequentially stacked, each of the first semiconductor chips including a circuit layer on a first surface of a first substrate, a through-silicon via passing through the first substrate, and a bump pad connected to the through-silicon via, and a second semiconductor chip on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer on a first surface of a second substrate, and a thermal path via in the second substrate.

公开(公告)号：US20220326301A1

公开(公告)日：2022-10-13

申请号：US17540745

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Yeonjin LEE ,  Minjung CHOI ,  Jimin CHOI

IPC: G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

公开(公告)号：US20220285189A1

公开(公告)日：2022-09-08

申请号：US17493198

申请日：2021-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjune BAE ,  Jimin CHOI ,  Hyungsik UM ,  Jeongjae BANG ,  Hyeonhui CHO

IPC: H01L21/677 ,  F16C35/00 ,  B66C9/04 ,  B61B12/02 ,  B61B3/02

Abstract: A steering device for an OHT according to some example embodiments of the present inventive concepts includes: an LM block; a steering plate fixedly installed to the LM block and provided with an insertion groove; a link installed in the insertion groove of the steering plate and tilted; a main bearing having an outer circumferential surface in contact with the link to reduce friction when the link is tilted; and a guide roller rotatably installed on a protrusion protruding from the link.

公开(公告)号：US20190157133A1

公开(公告)日：2019-05-23

申请号：US16238172

申请日：2019-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Dong LEE ,  KEUNNAM KIM ,  Dongryul LEE ,  Minseong CHOI ,  Jimin CHOI ,  YONG KWAN KIM ,  CHANGHYUN CHO ,  YOOSANG HWANG

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/108 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

公开(公告)号：US20250062193A1

公开(公告)日：2025-02-20

申请号：US18934456

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20240153919A1

公开(公告)日：2024-05-09

申请号：US18451197

申请日：2023-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong KIM ,  Jongmin LEE ,  Jimin CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3142 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08113 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip including a circuit layer on a first substrate, first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer, and a first upper bump pad and a second upper bump pad on a second surface of the first substrate, each of the first upper bump pad and the second upper bump pad connected to a corresponding one of the first through silicon vias. The package includes a second semiconductor chip including a circuit layer on a first surface of a second substrate, and second lower bump pads on the circuit layer on the second substrate. The package includes a first solder bump to bond the first upper bump pad and the second lower bump pad, and a plurality of second solder bumps to bond the second upper bump pad and the second lower bump pads.

公开(公告)号：US20240038675A1

公开(公告)日：2024-02-01

申请号：US18313491

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Joongwon SHIN ,  Sungyun WOO ,  Yeonjin LEE ,  Jongmin LEE ,  Sehyun HWANG

IPC: H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2223/54426

Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.

公开(公告)号：US20230116911A1

公开(公告)日：2023-04-13

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20230077803A1

公开(公告)日：2023-03-16

申请号：US17751740

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin CHOI ,  Jongmin LEE ,  Yeonjin LEE ,  Jeonil LEE ,  Juik LEE ,  Minjung CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.