公开(公告)号：US10902922B2

公开(公告)日：2021-01-26

申请号：US16412953

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Seo ,  Kui Han Ko ,  Jin-Young Kim ,  Il Han Park ,  Bong Soon Lim

IPC: G11C16/16 ,  G11C16/08

Abstract: A nonvolatile memory includes a first sub-block defined by a first string select line and a first word line; a second sub-block defined by a second string select line different from the first string select line and a second word line different from the first word line; a first vacant block defined by the first string select line and the second word line; and a second vacant block defined by the second string select line and the first word line. First data is programmed in the first sub-block with, second data is programmed in the second sub-block, and no data is programmed in the first vacant block and the second vacant block.

公开(公告)号：US10685713B2

公开(公告)日：2020-06-16

申请号：US16163968

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Jin-Young Kim ,  Kuihan Ko ,  Han Il Park ,  Bongsoon Lim

IPC: G11C16/04 ,  G11C16/14 ,  G06F3/06

Abstract: A storage device includes a nonvolatile memory device that includes memory blocks, each including memory cells, and a controller that receives a first write request from an external host device. Depending on the first write request, the controller transmits a first sanitize command to the nonvolatile memory device and transmits first write data and a first write command associated with the first write request to the nonvolatile memory device. The nonvolatile memory device is configured to sanitize first data previously written to first memory cells of a first memory block of the memory blocks in response to the first sanitize command. The nonvolatile memory device is further configured to write the first write data to second memory cells of the first memory block in response to the first write command.

公开(公告)号：US09786600B2

公开(公告)日：2017-10-10

申请号：US14970160

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC: H01L27/00 ,  H01L29/00 ,  H01L23/00 ,  H01L23/528 ,  H01L29/423 ,  H01L29/78 ,  H01L27/105 ,  H01L29/45 ,  H01L23/535 ,  H01L29/06 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

公开(公告)号：US09147440B2

公开(公告)日：2015-09-29

申请号：US13945418

申请日：2013-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Young Kim ,  Min-Gu Kang ,  Jae-Yun Lee ,  Beak-Hyung Cho

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C5/06 ,  G11C7/12 ,  G11C7/18

Abstract: A semiconductor memory device includes a plurality of functional bit lines, at least one dummy bit line, and a dummy bit line selection unit. The at least one dummy bit line is adjacent to an outermost bit line of the functional bit lines. The dummy bit line selection unit activates the at least one dummy bit line in response to a selection control signal of one of the plurality of functional bit lines that is not adjacent to the at least one dummy bit line. The semiconductor memory device may ensure a photo margin, so that the pattern size of the functional bit lines can be made uniform.

Abstract translation: 半导体存储器件包括多个功能位线，至少一个虚拟位线和虚拟位线选择单元。 至少一个虚拟位线与功能位线的最外位线相邻。 所述虚拟位线选择单元响应于与所述至少一个虚拟位线不相邻的所述多个功能位线之一的选择控制信号来激活所述至少一个虚拟位线。 半导体存储器件可以确保照相余量，使得功能位线的图案尺寸可以均匀。

公开(公告)号：US20150214230A1

公开(公告)日：2015-07-30

申请号：US14534853

申请日：2014-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Young Kim

IPC: H01L27/108 ,  H01L23/528

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a field region disposed therein that defines an active region of the substrate, the active region comprising a pillar-shaped bit line contact region having an upper surface disposed at a higher level than an upper surface of the field region. An interlayer insulating layer is disposed on the substrate and covers the field region. A bit line is disposed in a trench in the interlayer insulating layer above the pillar-shaped bit line contact region and electrically connected thereto.

Abstract translation: 半导体器件包括其中设置在其中的场区域的衬底，其限定衬底的有源区域，该有源区域包括柱形位线接触区域，其具有设置在比场区域的上表面更高的高度的上表面 。 层间绝缘层设置在基板上并覆盖场区域。 位线位于柱状位线接触区域上方的层间绝缘层的沟槽中，与其电连接。

公开(公告)号：US20250014664A1

公开(公告)日：2025-01-09

申请号：US18677544

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minji Cho ,  Hee-Woong Kang ,  Jin-Young Kim ,  Se Hwan Park ,  Ji-Sang Lee ,  Heewon Lee ,  Su Chang Jeon

IPC: G11C29/12 ,  G11C29/42

Abstract: Disclosed is a method of operating a storage device which includes a storage controller and a non-volatile memory device. The method includes providing, by the storage controller, the non-volatile memory device with a first request indicating a wordline selection operation of a target memory block, obtaining, by the non-volatile memory device, distribution information of a plurality of wordlines of the target memory block based on the first request, determining, by the non-volatile memory device, a deterioration wordline among the plurality of wordlines based on the distribution information, and providing, by the non-volatile memory device, the storage controller with wordline information indicating the deterioration wordline.

公开(公告)号：US12165721B2

公开(公告)日：2024-12-10

申请号：US18088046

申请日：2022-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangho Choi ,  Jin-Young Kim ,  Se Hwan Park ,  Il Han Park ,  Ji-Sang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US11574692B2

公开(公告)日：2023-02-07

申请号：US17359688

申请日：2021-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangho Choi ,  Jin-Young Kim ,  Se Hwan Park ,  Il Han Park ,  Ji-Sang Lee ,  Joonsuc Jang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

公开(公告)号：US11244721B2

公开(公告)日：2022-02-08

申请号：US16821265

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dojeon Lee ,  Dueung Kim ,  Jin-Young Kim

IPC: G11C11/56 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.

公开(公告)号：US11056193B2

公开(公告)日：2021-07-06

申请号：US16442672

申请日：2019-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Won Yun ,  Jin-Young Kim ,  Il-Han Park ,  Hyun Seo ,  Bong-Soon Lim

IPC: G11C16/16 ,  G11C16/04 ,  H01L27/11582 ,  G11C11/56

Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.