公开(公告)号：US10541033B2

公开(公告)日：2020-01-21

申请号：US15911208

申请日：2018-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Taeck Jung ,  Sang-Wan Nam ,  Jinwoo Park ,  Jaeyong Jeong

IPC: G11C16/10 ,  G11C16/20 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

公开(公告)号：US20170048615A1

公开(公告)日：2017-02-16

申请号：US15235639

申请日：2016-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beakkwon SON ,  Gangyoul Kim ,  Yangsu Kim ,  Chulmin Choi ,  Jinwoo Park ,  Gunhyuk Yoon ,  Namil Lee ,  Yonghoon Lee ,  Keunwon Jang ,  Seungyoon Heo

IPC: H04R3/04 ,  G10L19/16 ,  H04R29/00

CPC classification number: H04R3/04 ,  G10L19/167 ,  H03G3/3005 ,  H03G3/32 ,  H03G5/165 ,  H04R29/001 ,  H04R2430/01

Abstract: An audio processing method and an electronic device for supporting the same are provided. The audio signal processing method includes checking property information of an audio signal in response to a request for playing the audio signal; processing, when property information fulfils a first condition, the audio signal using the first method and, when the property information fulfils a second condition, the audio signal using the second method; and outputting the audio signal processed using one of the first and second methods through a speaker.

Abstract translation: 提供了音频处理方法和用于支持它的电子设备。 音频信号处理方法包括响应于播放音频信号的请求来检查音频信号的属性信息; 当属性信息满足第一条件时，使用第一方法的音频信号，并且当属性信息满足第二条件时，使用第二方法的音频信号; 并且通过扬声器输出使用第一和第二方法之一处理的音频信号。

公开(公告)号：US20250125205A1

公开(公告)日：2025-04-17

申请号：US18674416

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Kiseok Kim ,  Jinyoung Kim ,  Jihye Shim

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including first pads, a second semiconductor chip including second pads in contact with the first pads, and through-electrodes electrically connected to the second pads and extending to a rear surface opposite to the front surface, a dielectric layer covering at least portions of the respective first and second semiconductor chips and having an inner surface facing the first and second semiconductor chips and an outer surface opposite the inner surface, and bump structures on a portion of the outer surface of the dielectric layer and electrically connected to the through-electrodes. The dielectric layer includes inorganic particles, and polymer chains bonded to at least one sides of the respective inorganic particles and connected toward the inner surface and the outer surface via the inorganic particles.

公开(公告)号：US12260496B2

公开(公告)日：2025-03-25

申请号：US17971049

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inwoo Ha ,  Jinwoo Park

IPC: G06T15/60 ,  G06T5/92 ,  G06T7/579 ,  G06T19/00 ,  G06V10/60 ,  G06V10/74

Abstract: A method and device with light estimation are provided. A method performed by an electronic device includes generating a reference image based on image data acquired by capturing a reference object and based on a first image signal processing (ISP) setting, generating a background image based on raw image data acquired by capturing a real background in which the reference object is positioned and based on a second ISP setting, estimating light information corresponding to the background image using a light estimation model, rendering a virtual object image corresponding to the light information and the reference object, and training the light estimation model based on a difference between the reference image and the virtual object image.

公开(公告)号：US20240345758A1

公开(公告)日：2024-10-17

申请号：US18534379

申请日：2023-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Minji Kim ,  Sangwon Jung

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0688

Abstract: Disclosed is a storage device which includes nonvolatile memory devices each including a plurality of memory blocks, a memory controller that controls the nonvolatile memory devices, and a buffer memory that buffers data to be written in the nonvolatile memory devices. In an on-time erase operation, the memory controller controls the nonvolatile memory devices such that an erase operation is performed in a memory block for each of the nonvolatile memory devices. When an early erase condition is satisfied, the memory controller selects nonvolatile memory device among the nonvolatile memory devices and controls the selected nonvolatile memory device such that the erase operation is performed in a memory block of the selected nonvolatile memory device. When a free capacity of the buffer memory is smaller than a first threshold value, the memory controller determines that the early erase condition is satisfied.

公开(公告)号：US12069804B2

公开(公告)日：2024-08-20

申请号：US17560689

申请日：2021-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyujin Kwak ,  Jinwoo Park ,  Yonglak Cho ,  Jiwoo Lee

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0218 ,  H05K1/0243

Abstract: According to certain embodiments, an electronic device comprises: a housing including a first support member; a cover member coupled with and facing the first support member; a second support member coupled with and facing the first support member; a printed circuit board assembly disposed to face the first support member, the printed circuit board assembly having a part disposed between the first support member and the cover member and another part disposed between the first support member and the second support member; wherein the printed circuit board assembly comprises: a first circuit board including a first part disposed between the first support member and the cover member, and a second part disposed between the first support member and the second support member; a second circuit board disposed to at least partially face the first part and disposed between the first circuit board and the cover member; and an interposer board disposed to correspond to at least a part of an edge of the second circuit board and coupling the second circuit board with the first circuit board, and wherein the second support member biases a part of the edge of the second circuit board.

公开(公告)号：US20240203945A1

公开(公告)日：2024-06-20

申请号：US18419399

申请日：2024-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Jinwoo Park ,  Jaekyung Yoo ,  Teakhoon Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3135 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/17181 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US20240088092A1

公开(公告)日：2024-03-14

申请号：US18462610

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Woohyeong Kim ,  Jinwoo Park ,  Jayeon Lee ,  Chungsun Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a redistribution substrate having a first surface including first and a second regions and a second surface opposite to the first surface, and including a first redistribution layer, first and second semiconductor chips positioned in a first direction on the first region the redistribution substrate, each of the first and second semiconductor chips being electrically connected to the first redistribution layer, a first molding layer on the first region on the first and second semiconductor chips, a redistribution structure on the first molding layer and including a second redistribution layer, conductive posts on the first region and electrically connecting the first redistribution layer to the second redistribution layer, third and fourth semiconductor chips positioned in a second direction, intersecting the first direction, and each electrically connected to the second redistribution layer, and a second molding layer on the second region the redistribution substrate and on the third and fourth semiconductor chips.

公开(公告)号：US20240047418A1

公开(公告)日：2024-02-08

申请号：US18199553

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Gitae Park ,  Jinwoo Park

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L25/18 ,  H10B80/00 ,  H01L23/49833 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/16 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2924/181 ,  H01L2224/16227

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution patterns; a sub-semiconductor package including a sub-semiconductor package substrate and a first semiconductor chip that is on the sub-semiconductor package substrate, wherein the sub-semiconductor package substrate is on the redistribution layer and includes a plurality of first lower surface pads; and a second semiconductor chip on the redistribution layer and spaced apart from the sub-semiconductor package in a horizontal direction, wherein the second semiconductor chip includes a chip pad, wherein at least some of the plurality of redistribution patterns of the redistribution layer are overlapped with and electrically connected to the plurality of first lower surface pads of the sub-semiconductor package, respectively.

公开(公告)号：US11894338B2

公开(公告)日：2024-02-06

申请号：US17592947

申请日：2022-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jungho Park ,  Dahye Kim ,  Minjun Bae

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/94 ,  H01L23/3121 ,  H01L24/14 ,  H01L25/0657

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.