公开(公告)号：US20190043889A1

公开(公告)日：2019-02-07

申请号：US16157684

申请日：2018-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee PARK ,  Jong-Min LEE ,  Seon-Kyung KIM ,  Kee-Jeong RHO ,  Jin-hyun SHIN ,  Jong-Hyun PARK ,  Jin-Yeon WON

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

公开(公告)号：US20230024655A1

公开(公告)日：2023-01-26

申请号：US17858388

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangdon LEE ,  Joonsung KIM ,  Jiwon KIM ,  Jaeho KIM ,  Sukkang SUNG ,  Jong-Min LEE ,  Euntaek JUNG

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device may include a stack structure extending in a first direction and including gate electrodes vertically stacked on a substrate, selection structures horizontally spaced apart on the stack structure, an upper isolation structure between the selection structure and extending in the first direction on the stack structure, and vertical structures penetrating the stack structure and the selection structures. The vertical structures include first vertical structures arranged along the first direction and penetrating portions of the upper isolation structure. Each selection structure includes a selection gate electrode and a horizontal dielectric pattern that surrounds top, bottom, and sidewall surfaces of the selection gate electrode. Each selection gate electrode includes a line part extending in the first direction, and an electrode part vertically protruding from the line part and surrounding at least a portion of each first vertical structure.

公开(公告)号：US20200176556A1

公开(公告)日：2020-06-04

申请号：US16787426

申请日：2020-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE ,  HYONGSOO KIM ,  JONGRYUL JUN

IPC: H01L49/02

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

公开(公告)号：US20200083356A1

公开(公告)日：2020-03-12

申请号：US16570087

申请日：2019-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Bum LIM ,  Jong-Ryul JUN ,  Eun-A KIM ,  Jong-Min LEE

IPC: H01L29/66 ,  H01L49/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033

Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.

公开(公告)号：US20200073460A1

公开(公告)日：2020-03-05

申请号：US16466089

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE ,  Kwang-Eun GO ,  Kang-Sik KIM ,  Dong-Sub KIM ,  Young-San KIM ,  Won-Min KIM ,  Young-Hyun BAN ,  Min-Woo SONG ,  Chung-Hyo JUNG

IPC: G06F1/3206 ,  G06F1/08 ,  G06F1/324 ,  G06F1/20 ,  G06F1/3234

Abstract: Various embodiments of the present invention relate to an electronic device and a method for controlling heat generated on the surface of the electronic device. The electronic device may comprise a display and a processor, wherein the processor: displays, on the display, graphic elements at the request of a first application; during a first period of time, acquires first information corresponding to the graphic performance of the displayed graphic elements, and identifies a clock control level for controlling operation performance according to execution of the first application; and during a second period of time following the first period of time, identifies a clock value corresponding to the identified clock control level on the basis of the acquired first information, and controls the operation performance according to execution of the first application by using the identified clock value.

公开(公告)号：US20180199462A1

公开(公告)日：2018-07-12

申请号：US15846952

申请日：2017-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Jae MIN ,  Ji-Hun SEO ,  Sea-Young LEE ,  Jong-Min LEE ,  Hyo-Seok NA

IPC: H05K7/20 ,  H05K5/00 ,  H05K7/14

CPC classification number: H05K7/2039 ,  G06F1/1635 ,  G06F1/203 ,  H04M1/0202 ,  H04M1/0262 ,  H05K5/0086 ,  H05K7/1417

Abstract: A portable communication device is provided. The portable communication device includes a battery, a printed circuit board including one or more circuit devices driven using power from the battery, and a bracket including a first area for receiving the battery and a second area for receiving the printed circuit board, wherein a slit is formed in at least a portion of a boundary area of the first area and the second area to reduce heat spread. According to an embodiment of the present disclosure, in an electronic device, a heat-radiating structure is provided between a PCB and a bracket where a battery is seated, rerouting the path along which heat radiation from some circuit devices on the PCB flow to the battery to suppress a rise in temperature in the battery.

公开(公告)号：US20240282752A1

公开(公告)日：2024-08-22

申请号：US18509685

申请日：2023-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Yeonjin LEE ,  Jong-Min LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/3135 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/381

Abstract: Provided is a semiconductor package, including a semiconductor substrate including a plurality of first vias, a chip stack on the semiconductor substrate, the chip stack including first semiconductor chips on the semiconductor substrate, and a second semiconductor chip on an uppermost first semiconductor chip of the first semiconductor chips, and a mold layer on the semiconductor substrate and the chip stack, and exposing a top surface of the chip stack, wherein a first thickness of the semiconductor substrate is greater than a second thickness of each of the first semiconductor chips, wherein a third thickness of the second semiconductor chip is less than or equal to the second thickness of each of the first semiconductor chips, wherein the semiconductor substrate further includes lower substrate pads on a bottom surface of the semiconductor substrate, wherein each of the first semiconductor chips includes lower chip pads on a bottom surface of each of the first semiconductor chips, and wherein a first width of each of the lower substrate pads is greater than a second width of each of the lower chip pads.

公开(公告)号：US20240038830A1

公开(公告)日：2024-02-01

申请号：US18309126

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE

IPC: H10B12/00

CPC classification number: H01L28/90 ,  H10B12/482 ,  H10B12/315

Abstract: The semiconductor device is provided. The semiconductor device comprises a substrate; a plurality of lower electrodes on the substrate and arranged in a honeycomb structure; and a supporter connecting the plurality of lower electrodes to each other, wherein the supporter has a plurality of supporter holes defined therein, wherein each of the plurality of supporter holes exposes at least a portion of each of the plurality of lower electrodes, wherein the supporter includes: a plurality of first extensions extending in a first direction; and a plurality of second extensions extending in a second direction so as to intersect the plurality of first extensions, wherein each of the plurality of first extensions has first and second sidewalls, wherein each of the plurality of second extensions has third and fourth sidewalls, wherein each of the first to fourth sidewalls includes a convex portion and a concave portion.

公开(公告)号：US20230012115A1

公开(公告)日：2023-01-12

申请号：US17570874

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho KIM ,  Jiwon KIM ,  Joonsung KIM ,  Sukkang SUNG ,  Sangdon LEE ,  Jong-Min LEE ,  Euntaek JUNG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

公开(公告)号：US20210183994A1

公开(公告)日：2021-06-17

申请号：US17156773

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min LEE ,  HYONGSOO KIM ,  JONGRYUL JUN

IPC: H01L49/02

Abstract: A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.