公开(公告)号：US20240315013A1

公开(公告)日：2024-09-19

申请号：US18406454

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun CHOI ,  Seok Han PARK ,  Bo Won YOO ,  Ki Seok LEE ,  Jin Woo HAN

IPC: H10B12/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B12/482 ,  H01L23/5226 ,  H01L23/5283 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a peri-gate structure on a substrate, a first bonding pad on the peri-gate structure, a shielding conductive pattern on the first bonding pad, a second bonding pad between the shielding conductive pattern and the first bonding pad and contacting the first bonding pad, a bit line on the shielding conductive pattern extending in a first direction, an active pattern on the bit line and including a lower surface and an upper surface, and a first side wall and a second side wall opposite to each other in the first direction, the lower surface of the active pattern being connected to the bit line, a word line on the first side wall of the active pattern, and extends in a third direction, and a data storage pattern on the active pattern, and is connected to the upper surface of the active pattern.

公开(公告)号：US20230371243A1

公开(公告)日：2023-11-16

申请号：US18101613

申请日：2023-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok LEE ,  Keun Nam KIM ,  Seok Han PARK

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device includes a peripheral gate structure disposed on a substrate, a bit line disposed on the peripheral gate structure and extending in a first direction, a shielding structure disposed adjacent to the bit line on the peripheral gate structure and extending in the first direction, a first word line disposed on the bit line and the shielding structure and extending in a second direction, a second word line disposed on the bit line and the shielding structure, extending in the second direction, and spaced apart from the first word line in the first direction, first and second active patterns disposed on the bit line and disposed between the first and second word lines, and contact patterns connected to the first and second active patterns.

公开(公告)号：US20220223732A1

公开(公告)日：2022-07-14

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H01L27/108

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US20190252393A1

公开(公告)日：2019-08-15

申请号：US16391888

申请日：2019-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho ln LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC: H01L27/11 ,  H01L27/108 ,  H01L29/10 ,  H01L21/8238

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20170278847A1

公开(公告)日：2017-09-28

申请号：US15461726

申请日：2017-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Oh KIM ,  Chan Sic YOON ,  Ki Seok LEE ,  Yong Jae KIM

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/10814 ,  H01L23/528 ,  H01L27/10844 ,  H01L27/10852 ,  H01L29/0696

Abstract: A semiconductor device includes a substrate including a cell area and a background area, the background area surrounding the cell area, a plurality of active patterns in the cell area along a first direction, the active patterns being defined by a device isolation layer, and a background pattern filling the background area to surround the cell area, wherein the active patterns include a first active pattern most adjacent to an edge of the cell area, and a second active pattern separated from the first active pattern in a second direction intersecting the first direction, the second active pattern being separated from the background area.

公开(公告)号：US20240371994A1

公开(公告)日：2024-11-07

申请号：US18775518

申请日：2024-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae RYU ,  Sang Hoon UHM ,  Ki Seok LEE ,  Min Su LEE ,  Won Sok LEE ,  Min Hee CHO

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US20210408004A1

公开(公告)日：2021-12-30

申请号：US17469340

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho LEE ,  Eun A KIM ,  Ki Seok LEE ,  Jay-Bok CHOI ,  Keun Nam KIM ,  Yong Seok AHN ,  Jin-Hwan CHUN ,  Sang Yeon HAN ,  Sung Hee HAN ,  Seung Uk HAN ,  Yoo Sang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

公开(公告)号：US20190088659A1

公开(公告)日：2019-03-21

申请号：US16183826

申请日：2018-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Seok LEE ,  Jeong Seop SHIM ,  Mi Na LEE ,  Augustin Jinwoo HONG ,  Je Min PARK ,  Hye Jin SEONG ,  Seung Min OH ,  Do Yeong LEE ,  Ji Seung LEE ,  Jin Seong LEE

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10891

Abstract: A semiconductor device includes a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other, and a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, wherein the plurality of pillar patterns include first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, a shape of a horizontal cross section of the first pillar patterns being different from a shape of a horizontal cross section of the second pillar patterns.

公开(公告)号：US20180175038A1

公开(公告)日：2018-06-21

申请号：US15712410

申请日：2017-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho In LEE ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Wook JUNG ,  Jinwoo Augustin HONG ,  Je Min PARK ,  Ki Seok LEE ,  Ju Yeon JANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/12 ,  H01L29/43 ,  H01L29/66

CPC classification number: H01L27/10823 ,  H01L21/762 ,  H01L21/76834 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1248 ,  H01L29/432 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7869

Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.

公开(公告)号：US20170213724A1

公开(公告)日：2017-07-27

申请号：US15291415

申请日：2016-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Sic YOON ,  Ki Seok LEE ,  Dong Oh KIM

IPC: H01L21/027

CPC classification number: H01L21/0276 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823481

Abstract: A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.