公开(公告)号：US20150017743A1

公开(公告)日：2015-01-15

申请号：US14498465

申请日：2014-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho LEE ,  Ki Joon KIM ,  Se Woong PARK

IPC: H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/10888 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82

Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

Abstract translation: 存储器件及其制造方法包括：包括单元区域和外围电路区域的衬底，在单元区域上的数据存储，在数据存储器上并耦合到数据存储器的第一位线，耦合到外围电路区域上的外围晶体管的第一触点 以及在第一触点上并耦合到第一触点的第二位线。 第二位线可以各自具有低于数据存储器的最低表面的最下表面。

公开(公告)号：US20250079302A1

公开(公告)日：2025-03-06

申请号：US18444990

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungjae BAE ,  Jin-Wook YANG ,  Seung Pil KO ,  Yongjae KIM ,  Junho PARK ,  Kilho LEE

IPC: H01L23/528 ,  H01L23/48 ,  H01L29/417 ,  H10B61/00

Abstract: A semiconductor device includes a substrate having a top surface and a bottom surface opposite to each other, a gate structure on the top surface of the substrate, a plurality of source/drain patterns on the top surface of the substrate and on opposite sides of the gate structure, a backside conductive line on the bottom surface of the substrate and electrically connected to at least one of the gate structure or a first source/drain pattern of the source/drain patterns, and a magnetic tunnel junction pattern electrically connected to a second source/drain pattern of the source/drain patterns.

公开(公告)号：US20250072005A1

公开(公告)日：2025-02-27

申请号：US18629542

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho LEE ,  Yongjae Lee

IPC: H10B61/00 ,  B64D47/00 ,  H01L25/065 ,  H10B80/00

Abstract: Provided is a semiconductor device including a logic region including a circuit, a first memory region controlled by the logic region and having a first storage capacity, the first memory region including a plurality of first memory cells, and a second memory region controlled by the logic region and having a second storage capacity greater than the first storage capacity, the second memory region including a plurality of second memory cells, wherein each of the plurality of first memory cells and each of the plurality of second memory cells includes a magnetic memory element, and wherein an operating speed of the first memory region is faster than an operating speed of the second memory region.

公开(公告)号：US20240313782A1

公开(公告)日：2024-09-19

申请号：US18410351

申请日：2024-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Koog KIM ,  Junhoe KIM ,  Gyuyoung PARK ,  Gwanhyeob KOH ,  Kilho LEE

IPC: H03K19/23 ,  H03K19/18

CPC classification number: H03K19/23 ,  H03K19/18

Abstract: An operating method of a chaotic computer including a chaotic logic device includes setting a first initial value based on a first initial state corresponding to a first logical operation, applying the set first initial value to the chaotic logic device, setting a first input value to be applied to the chaotic logic device based on first input data, applying the first input value to the chaotic logic device, generating a chaos signal to have the chaotic logic device operate in a chaotic mode, applying the chaos signal to the chaotic logic device, and measuring a first output value from the chaotic logic device operating based on the first input value and the chaos signal, and generating first output data based on the first output value. The chaotic logic device includes a magnetic thin film configured to have spin soliton formed therein.

公开(公告)号：US20210257404A1

公开(公告)日：2021-08-19

申请号：US17028034

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Woojin KIM

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/12 ,  H01L21/768

Abstract: An embedded device includes a first insulation layer, a second insulation layer on the first insulation layer, a lower electrode contact in the first insulation layer in a first region, a first structure, having a lower electrode, a magnetic tunnel junction, and an upper electrode, in the second insulation layer and contacting the lower electrode contact, a first metal wiring structure through the first and second insulation layers in a second region, a third insulation layer on the second insulation layer, a bit line structure through the third insulation layer and the second insulation layer in the first region, the bit line structure having a first height and contacting the upper electrode, and a second metal wiring structure through the third insulation layer in the second region, the second metal wiring structure contacting the first metal wiring structure, and having a second height lower than the first height.

公开(公告)号：US20210151502A1

公开(公告)日：2021-05-20

申请号：US16892583

申请日：2020-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woojin KIM ,  Yongjae KIM ,  Kilho LEE

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02

Abstract: A magnetoresistive random access memory device including a first insulating interlayer on a substrate; lower electrode contacts passing through the first insulating interlayer; first structures on the lower electrode contacts, respectively, each of the first structures including a stacked lower electrode, magnetic tunnel junction (MTJ) structure, and upper electrode; a second insulating interlayer on the first structures and the first insulating interlayer, the second insulating interlayer filling a space between the first structures; a third insulating interlayer directly contacting the second insulating interlayer, the third insulating interlayer having a dielectric constant lower than a dielectric constant of the second insulating interlayer; and a bit line passing through the third insulating interlayer and the second insulating interlayer, the bit line contacting the upper electrode of one of the first structures.

公开(公告)号：US20210104575A1

公开(公告)日：2021-04-08

申请号：US16848010

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Gwanhyeob KOH

IPC: H01L27/22 ,  G11C11/56 ,  G11C11/02

Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.

公开(公告)号：US20190088656A1

公开(公告)日：2019-03-21

申请号：US15959366

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Hyun KIM ,  Seung Pil KO ,  Hyunchul SHIN ,  Kilho LEE

IPC: H01L27/105 ,  G11C11/16 ,  H01L43/02

Abstract: Disclosed are data storage devices and methods of manufacturing the same. The methods may include providing a substrate including a cell region and a peripheral circuit region, forming a data storage layer on the cell region and the peripheral circuit region of the substrate, selectively forming a mask layer on a portion of the data storage layer that is formed on the peripheral circuit region, forming a top electrode layer on the data storage layer and the mask layer, patterning the top electrode layer to form a plurality of top electrodes on the cell region, and patterning the data storage layer using the plurality of top electrodes as an etch mask to form a plurality of data storage parts on the cell region. While patterning the top electrode layer, the mask layer on the peripheral circuit region may serve as an etch stop layer.

公开(公告)号：US20180358408A1

公开(公告)日：2018-12-13

申请号：US15828937

申请日：2017-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho LEE ,  Gwanhyeob Koh ,  Hongsoo Kim ,  Junhee Lim ,  Chang-Hoon Jeon

IPC: H01L27/22 ,  G11C5/02 ,  G11C11/16 ,  H01L27/24 ,  H01L49/02 ,  H01L43/08

CPC classification number: H01L27/228 ,  G11C5/025 ,  G11C11/005 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/224 ,  H01L27/2436 ,  H01L27/2463 ,  H01L28/20 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.