公开(公告)号：US08762052B2

公开(公告)日：2014-06-24

申请号：US13930389

申请日：2013-06-28

Applicant: Samsung Electronics Co. Ltd.

Inventor： Hyun-Suk Min ,  Hee Jung ,  Kwang-Soo Kim ,  Jin-Won Kim

IPC: G06F17/30 ,  G01C21/00

CPC classification number: G01C21/00 ,  G01C21/3647

Abstract: A method and a terminal for providing a route in a navigation system using a satellite image are provided. The terminal includes a route calculation unit for calculating a route from a current location to a destination when a user inputs the destination, a satellite image requesting unit for requesting a satellite image server for satellite images corresponding to locations on the route and for downloading the requested satellite images, a satellite image storage unit for storing the downloaded satellite images, and a controller for retrieving a satellite image corresponding to the current location from the satellite image storage unit and for displaying the retrieved satellite image simultaneously while downloading the satellite images corresponding to the locations on the route.

Abstract translation: 提供了一种使用卫星图像在导航系统中提供路线的方法和终端。 终端包括路由计算单元，用于当用户输入目的地时计算从当前位置到目的地的路线;卫星图像请求单元，用于请求卫星图像服务器，用于与路线上的位置相对应的卫星图像，并且下载所请求的 卫星图像，用于存储下载的卫星图像的卫星图像存储单元，以及用于从卫星图像存储单元检索与当前位置相对应的卫星图像并用于同时显示所检索的卫星图像的控制器，同时下载对应于卫星图像的卫星图像 路线上的位置。

公开(公告)号：US20250048643A1

公开(公告)日：2025-02-06

申请号：US18588712

申请日：2024-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suseong Noh ,  Sangwoo Han ,  Kwang-Soo Kim ,  Ilho Myeong

IPC: H10B51/20 ,  H10B51/30 ,  H10B51/40

Abstract: The present disclosure relates to a semiconductor device and a data storage system including the device. The semiconductor device has a substrate including a cell array region and a contact region. In the cell array region the semiconductor device has a first horizontal conductive layer, a gate stacking structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate. A channel structure extends in a direction crossing into the substrate by penetrating the gate stacking structure in the cell array region, and includes a channel layer connected to the substrate. Surrounding the channel layer is a ferroelectric layer. The first horizontal conductive layer is not in direct contact with the channel layer due to a dummy pattern positioned on the first horizontal conductive layer and disposed between the substrate and the ferroelectric layer.

公开(公告)号：US20250022787A1

公开(公告)日：2025-01-16

申请号：US18440215

申请日：2024-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Kwang-Soo Kim ,  Jaesic Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip, a second semiconductor chip, and a connection die. A hybrid bonding may be established between the connection die and the first semiconductor chip and between the connection die and the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having first and second surfaces. The first surface is closer than the second surface to the connection die. The second semiconductor chip includes a second semiconductor substrate having third and fourth surfaces. The third surface is closer than the fourth surface to the connection die. The first and second semiconductor chips further include a power distribution wiring layer on the second surface of the first semiconductor chip and the fourth surface of the second semiconductor substrate.

公开(公告)号：US11839091B2

公开(公告)日：2023-12-05

申请号：US17011156

申请日：2020-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Bonghyun Choi ,  Siwan Kim

IPC: H10B43/20 ,  H10B69/00

CPC classification number: H10B69/00 ,  H10B43/20

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

公开(公告)号：US11075217B2

公开(公告)日：2021-07-27

申请号：US16261694

申请日：2019-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Soo Kim ,  Tae-Seok Jang

IPC: H01L23/52 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

Abstract: A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction. Each of the even cell blocks includes second conductive line structures having substantially the same shape as the first conductive line structures. The odd block pad structure is connected to first edge portions of the first conductive line structures. The even block pad structure is connected to second edge portions, opposite the first edge portions, of the second conductive line structures. Each of the odd cell blocks and the even cell blocks has a first width in a third direction. Each of the odd and even block pad structures is formed on a region of a substrate having a second width greater than the first width in the third direction.

公开(公告)号：US10811430B2

公开(公告)日：2020-10-20

申请号：US16272288

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Kwang-Soo Kim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/28

Abstract: Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.

公开(公告)号：US20140239795A1

公开(公告)日：2014-08-28

申请号：US14151166

申请日：2014-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOK-RAE KIM ,  Hashimoto Kohei ,  Won-Don Joo ,  Kwang-Soo Kim ,  Byeong-Hwan Jeon ,  Sue-Jin Cho

IPC: H01J61/02

CPC classification number: H01J61/025 ,  G03F7/70016 ,  G03F7/70175 ,  H01J61/545 ,  H01J61/86 ,  H01J65/042

Abstract: Provided are a light source device and a semiconductor manufacturing apparatus including the same. The light source device includes a light-emitting lamp. The light source device includes a laser generator configured to generate and direct a laser beam to the light-emitting lamp. The light source device includes a recycling optical element configured to redirect the laser beam to the light-emitting lamp. The recycling optical element includes a first recycling optical modulator configured to change the phase of the laser beam.

Abstract translation: 提供一种光源装置和包括该光源装置的半导体制造装置。 光源装置包括发光灯。 光源装置包括：激光发生器，被配置为产生并将激光束定向到发光灯。 光源装置包括被配置为将激光束重定向到发光灯的再循环光学元件。 回收光学元件包括被配置为改变激光束的相位的第一再循环光学调制器。

公开(公告)号：US12207471B2

公开(公告)日：2025-01-21

申请号：US17459887

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hae-Min Lee ,  Kwang-Soo Kim ,  Sun-Il Shim

IPC: H10B43/35 ,  G11C5/06 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

公开(公告)号：US20250006625A1

公开(公告)日：2025-01-02

申请号：US18437638

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Kwang-Soo Kim ,  Jaesic Lee

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package is provided. The semiconductor package includes a first semiconductor chip, which includes: a first semiconductor substrate having a first surface and a second surface, which are opposite to each other; a circuit layer on the first surface; a first interconnection layer on the circuit layer; a second interconnection layer on the second surface; a penetration via extending from the second surface into the first semiconductor substrate; and a capacitor extending from the second surface toward the first surface. The capacitor is spaced apart from the penetration via in a first direction that is parallel to the first surface of the first semiconductor substrate.

公开(公告)号：US10964638B2

公开(公告)日：2021-03-30

申请号：US16704499

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Soo Kim

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/115 ,  H01L27/11582 ,  H01L49/02

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.