公开(公告)号：US20190043860A1

公开(公告)日：2019-02-07

申请号：US16158797

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US09613811B2

公开(公告)日：2017-04-04

申请号：US14525467

申请日：2014-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Jik Baek ,  Sang-Jine Park ,  Bo-Un Yoon ,  Young-Sang Youn ,  Ji-Min Jeong ,  Ji-Hoon Cha

IPC: H01L21/338 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/266 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66575

Abstract: A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask.

公开(公告)号：US20150162197A1

公开(公告)日：2015-06-11

申请号：US14525467

申请日：2014-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Jik BAEK ,  Sang-Jine Park ,  Bo-Un Yoon ,  Young-Sang Youn ,  Ji-Min Jeong ,  Ji-Hoon Cha

IPC: H01L21/266 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L21/266 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66575

Abstract: A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask.

Abstract translation: 在基板上依次形成第一保护层，掩模层，第二保护层和光致抗蚀剂层。 通过部分去除光致抗蚀剂层形成光致抗蚀剂图案。 通过使用光致抗蚀剂图案依次蚀刻第二保护层，掩模层和第一保护层来形成离子注入掩模。 离子注入掩模暴露衬底。 将杂质植入由离子注入掩模暴露的衬底的上部。

公开(公告)号：US10734380B2

公开(公告)日：2020-08-04

申请号：US16158797

申请日：2018-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：US09947672B2

公开(公告)日：2018-04-17

申请号：US15371751

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20170084617A1

公开(公告)日：2017-03-23

申请号：US15371751

申请日：2016-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US09466697B2

公开(公告)日：2016-10-11

申请号：US14721004

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Abstract translation: 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

公开(公告)号：US09040415B2

公开(公告)日：2015-05-26

申请号：US14286108

申请日：2014-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Young-Sang Youn ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Byung-Kwon Cho ,  Ji-Hoon Cha

IPC: H01L21/4763 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L2221/1063

Abstract: A method for forming a trench includes etching an oxide layer to form a trench therein, conformally forming a first reaction layer along a surface of the trench, the first reaction layer including a first region on an upper portion of the trench and a second region on a lower portion of the trench, forming a barrier layer by reacting a first amount of etching gas with the first region of the first reaction layer, and etching the oxide layer on a lower portion of the second region by reacting a second amount of etching gas with the second region of the first reaction layer, the second amount of etching gas being greater than the first amount of etching gas.

Abstract translation: 一种用于形成沟槽的方法包括蚀刻氧化物层以在其中形成沟槽，沿着沟槽的表面共形形成第一反应层，第一反应层包括沟槽上部的第一区域和第二区域 沟槽的下部，通过使第一量的蚀刻气体与第一反应层的第一区域反应形成阻挡层，并且通过使第二量的蚀刻气体反应来蚀刻第二区域的下部的氧化物层 与第一反应层的第二区域相比，第二量的蚀刻气体大于第一量的蚀刻气体。

公开(公告)号：US20140322881A1

公开(公告)日：2014-10-30

申请号：US14326760

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Abstract translation: 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。