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    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
    14.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210020543A1

    公开(公告)日：2021-01-21

    申请号：US16794782

    申请日：2020-02-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hakseung Lee ,  Jinnam Kim ,  Kwangjin Moon ,  Eunji Kim ,  Taeseong Kim ,  Sangjun Park

    IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768 ,  H01L23/00

    Abstract: A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.

    Integrated circuit devices with capacitor and methods of manufacturing the same
    15.
    发明授权
    Integrated circuit devices with capacitor and methods of manufacturing the same 有权
    具有电容器的集成电路器件及其制造方法

    公开(公告)号：US09111953B2

    公开(公告)日：2015-08-18

    申请号：US13790773

    申请日：2013-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongkyun Park ,  Mansug Kang ,  Hyongsoo Kim ,  Sangjun Park ,  Kukhan Yoon

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  H01L28/92

    Abstract: An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer.

    Abstract translation: 提供具有电容器的集成电路器件和形成集成电路器件的方法。 所述方法可以包括在模具层中的孔的内表面上形成第一低电容电极图案。 第一较低电容器电极图案可以具有中空圆柱形形状和在上表面中的开口。 该方法还可以包括形成插入开口的第二下电容器电极图案，并且第二下电容器电极图案的上表面可以是平面的。 第一和第二下部电容器电极图案可以包括包括空隙的下部电容器电极。 此外，该方法可以包括去除模具层以暴露下电容器电极，在下电容器电极上形成介电层，并在电介质层上形成上电容器电极层。

    SEMICONDUCTOR CHIP STRUCTURE
    16.
    发明申请
    SEMICONDUCTOR CHIP STRUCTURE 有权

    公开(公告)号：US20250087531A1

    公开(公告)日：2025-03-13

    申请号：US18955826

    申请日：2024-11-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangjun Park ,  Byungkyu Kim ,  Eunji Kim ,  Seungwoo Paek ,  Sungdong Cho

    IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer.

    Semiconductor devices having bonding structures with bonding pads and metal patterns
    18.
    发明授权
    Semiconductor devices having bonding structures with bonding pads and metal patterns 有权

    公开(公告)号：US11532581B2

    公开(公告)日：2022-12-20

    申请号：US17158450

    申请日：2021-01-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uidam Jung ,  Hyoungyol Mun ,  Sangjun Park ,  Kyuha Lee

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

    Structure of electronic device for optimizing performance of antenna and method thereof
    20.
    发明授权
    Structure of electronic device for optimizing performance of antenna and method thereof 有权

    公开(公告)号：US11063358B2

    公开(公告)日：2021-07-13

    申请号：US16899838

    申请日：2020-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungjoon Yu ,  Youngjun Park ,  Myungjin Kang ,  Youngkwon Lee ,  Yongwoon Moon ,  Sangjun Park

    IPC: H01Q5/335 ,  H04W88/06 ,  H01Q23/00 ,  H04W84/04

    Abstract: An electronic device for supporting carrier aggregation (CA) is provided. The electronic device includes a radio frequency integrated circuit (RFIC) including a plurality of mixers and a feedback circuit, at least one antenna, a coupler disposed between the RFIC and the at least one antenna to transfer a reflected signal of a transmission signal to the feedback circuit, and at least one processor operatively connected to the RFIC, wherein the at least one processor may identify whether there is a mixer which is not in use among the plurality of mixers, when the first mixer which is not in use among the plurality of mixers is identified, perform antenna impedance tuning through a first mixer and the feedback circuit, and when the plurality of mixers are all in use, perform the antenna impedance tuning through a second mixer assigned to a secondary cell (Scell) among the plurality of mixers and the feedback circuit.

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