公开(公告)号：US11714579B2

公开(公告)日：2023-08-01

申请号：US17828176

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonkyoo Lee ,  Jeongdon Ihm ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G06F3/06 ,  G06F1/06 ,  G06F13/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0613 ,  G06F3/0679 ,  G06F13/1668 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

公开(公告)号：US20230091026A1

公开(公告)日：2023-03-23

申请号：US17994296

申请日：2022-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: H03L7/081 ,  H03L7/085 ,  H03K5/133 ,  G11C7/22

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

公开(公告)号：US20250096825A1

公开(公告)日：2025-03-20

申请号：US18772352

申请日：2024-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daechul Jeong ,  Seonkyoo Lee ,  Taesung Lee ,  Tongsung Kim

IPC: H04B1/04 ,  H03K19/0185

Abstract: A data signal transmitter includes a standby voltage generator, which is configured to selectively output: (i) a data signal during an active operation mode, and (ii) first and second different standby voltages during a standby operation mode, and a repeater block. The repeater block includes: a first CMOS inverter configured to receive the first standby voltage during the standby operation mode, and a second CMOS inverter configured to receive the second standby voltage during the standby operation mode.

公开(公告)号：US20250095755A1

公开(公告)日：2025-03-20

申请号：US18932736

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

IPC: G11C16/32 ,  G11C16/04 ,  G11C29/02

Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal from the memory controller, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously.

公开(公告)号：US20250095754A1

公开(公告)日：2025-03-20

申请号：US18804617

申请日：2024-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K5/156

Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation.

公开(公告)号：US11522550B2

公开(公告)日：2022-12-06

申请号：US17077891

申请日：2020-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/22 ,  H03K5/133 ,  H03L7/081 ,  H03L7/085 ,  G11C29/02

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

公开(公告)号：US11522261B2

公开(公告)日：2022-12-06

申请号：US16730277

申请日：2019-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jindo Byun ,  Seonkyoo Lee ,  Hyunjin Kim

IPC: H01P3/16 ,  H01P3/08 ,  H01L23/538 ,  G11C16/10 ,  H01P1/20

Abstract: A multi-mode transmission line includes a first and second conductive layers, first and second waveguide walls, a strip line, and a blind conductor. The second conductive layer that is formed over the first conductive layer. The first waveguide wall is elongated in a first direction and is in contact with the first conductive layer and the second conductive layer in a vertical direction. The second waveguide wall is elongated in the first direction parallel to the first waveguide wall and is in contact with the first conductive layer and the second conductive layer in the vertical direction. The strip line is formed between the first and second conductive layers and between the first and second waveguide walls. The blind conductor is connected to one of the first conductive layer, the second conductive layer, the first waveguide wall, or the second waveguide wall.

公开(公告)号：US09767873B2

公开(公告)日：2017-09-19

申请号：US15198564

申请日：2016-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G06F11/10 ,  G11C16/32

CPC classification number: G11C7/22 ,  G06F11/10 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/32

Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.

公开(公告)号：US09601171B2

公开(公告)日：2017-03-21

申请号：US14665148

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunjin Kim ,  Seonkyoo Lee ,  Jeongdon Ihm ,  Youngjin Jeon

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G11C16/06 ,  G11C16/32

CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C16/06 ,  G11C16/32

Abstract: A storage device includes a nonvolatile memory, and a memory controller adapted to control the nonvolatile memory and to transmit a first timing signal to the nonvolatile memory at a read operation. The nonvolatile memory includes a nonvolatile memory device adapted to output read data and a second timing signal in response to the first timing signal, and a retiming circuit adapted to detect a locking delay according to the first timing signal, to produce a third timing signal from the second timing signal using the detected locking delay, to retime the read data by latching the read data in synchronization with the third timing signal and to output the third timing signal and the retimed read data to the memory controller.

公开(公告)号：US20250104749A1

公开(公告)日：2025-03-27

申请号：US18604593

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongho Shin ,  Kangyoon Lee ,  Seonkyoo Lee ,  Junha Lee

IPC: G11C7/22

Abstract: A method of calibrating impedance of a memory device including a data transmitter includes: outputting a comparison signal by comparing a power supply voltage and a reference voltage, the power supply voltage being supplied to the data transmitter when the data transmitter is driven; storing a voltage level of the reference voltage when the comparison signal changes logical state; adjusting the reference voltage based on the comparison signal such that the voltage level of the reference voltage increases or decreases; and calibrating an output impedance of the memory device based on a digital code corresponding to an average reference voltage level, the average reference voltage level being obtained by averaging a prescribed number of voltage levels of the reference voltage stored as a result of repeatedly outputting the comparison signal, storing the voltage level of the reference voltage, and adjusting the reference voltage.