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11.发明公开公开(公告)号：US20240161850A1
公开(公告)日：2024-05-16
申请号：US18362130
申请日：2023-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byeongho Kim , Shinhaeng Kang , Suk Han Lee , Hweesoo Kim , Kyomin Sohn
CPC classification number: G11C29/18 , G11C29/1201 , G11C2029/1202 , G11C2029/1204
Abstract: A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.
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公开(公告)号：US11822898B2
公开(公告)日：2023-11-21
申请号：US17547991
申请日：2021-12-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng Kang , Seongil O
CPC classification number: G06F7/48 , G06F13/16 , G11C7/1048 , G11C2207/2272
Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.
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13.发明授权公开(公告)号：US11635962B2
公开(公告)日：2023-04-25
申请号：US16814462
申请日：2020-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sukhan Lee , Shinhaeng Kang , Namsung Kim , Seongil O , Hak-Soo Yu
Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.
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公开(公告)号：US11593625B2
公开(公告)日：2023-02-28
申请号：US16160444
申请日：2018-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng Kang , Seungwon Lee
Abstract: Provided is a processor implemented method that includes performing training or an inference operation with a neural network by obtaining a parameter for the neural network in a floating-point format, applying a fractional length of a fixed-point format to the parameter in the floating-point format, performing an operation with an integer arithmetic logic unit (ALU) to determine whether to round off a fixed point based on a most significant bit among bit values to be discarded after a quantization process, and performing an operation of quantizing the parameter in the floating-point format to a parameter in the fixed-point format, based on a result of the operation with the ALU.
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公开(公告)号：US11550543B2
公开(公告)日：2023-01-10
申请号：US16691033
申请日：2019-11-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng Kang , Seongil O
Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.
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Patent Agency Ranking
公开(公告)号：US12182409B2
公开(公告)日：2024-12-31
申请号：US17938789
申请日：2022-10-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Shinhaeng Kang , Sukhan Lee , Hweesoo Kim , Kyomin Sohn
IPC: G06F3/06
Abstract: A memory device supporting a processing-in-memory (PIM) protocol includes a mode register set (MRS) configured to store a first parameter code and a second parameter code regarding the PIM protocol in a first register and a second register, respectively. The first parameter code includes a PIM protocol change code indicating whether a PIM protocol change related to an old version PIM protocol is supported, and the second parameter code includes a PIM protocol code for setting a current operation PIM protocol from among a plurality of PIM protocols. The memory device further includes a PIM circuit configured to perform an internal processing operation based on the current operation PIM protocol.
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公开(公告)号：US12106107B2
公开(公告)日：2024-10-01
申请号：US18194174
申请日：2023-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sukhan Lee , Shinhaeng Kang , Namsung Kim , Seongil O , Hak-Soo Yu
CPC classification number: G06F9/30145 , G06F9/321 , G06F15/7821
Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.
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公开(公告)号：US12099839B2
公开(公告)日：2024-09-24
申请号：US17314476
申请日：2021-05-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yuhwan Ro , Shinhaeng Kang , Seongil O , Seungwoo Seo
CPC classification number: G06F9/3001 , G06F9/30079 , G06F9/30101 , G06F9/5016 , G06F12/06 , G06F13/1621 , G06F15/7821 , H03K19/1737
Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.
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19.发明授权公开(公告)号：US11880317B2
公开(公告)日：2024-01-23
申请号：US17845441
申请日：2022-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhaeng Kang , Sukhan Lee
CPC classification number: G06F13/1668 , G06F3/0655 , G06F13/4027 , G06F9/3877
Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.
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20.发明授权公开(公告)号：US11663008B2
公开(公告)日：2023-05-30
申请号：US16814462
申请日：2020-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sukhan Lee , Shinhaeng Kang , Namsung Kim , Seongil O , Hak-Soo Yu
CPC classification number: G06F9/30145 , G06F9/321 , G06F15/7821
Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.
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