公开(公告)号：US11625302B2

公开(公告)日：2023-04-11

申请号：US16692161

申请日：2019-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Min Kang ,  Dongku Kang ,  Su Chang Jeon ,  Won-Taeck Jung

IPC: G11C11/34 ,  G06F11/14 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0882 ,  G11C11/56 ,  G11C11/409 ,  G11C11/408 ,  G11C11/4074 ,  G06F12/0873

Abstract: A method of programming a nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

公开(公告)号：US11380404B2

公开(公告)日：2022-07-05

申请号：US17099678

申请日：2020-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chang Jeon ,  Seung Bum Kim ,  Ji Young Lee

IPC: G11C16/24 ,  G11C16/12 ,  G11C16/26

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

公开(公告)号：US12182419B2

公开(公告)日：2024-12-31

申请号：US18184319

申请日：2023-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woohyun Kang ,  Su Chang Jeon ,  Suhyun Kim ,  Hyuna Kim ,  Youngdeok Seo ,  Hyunkyo Oh ,  Donghoo Lim ,  Byungkwan Chun

IPC: G06F11/00 ,  G06F3/06

Abstract: Disclosed is a method of operating a storage controller which communicates with a non-volatile memory device. The method includes providing a read command to the non-volatile memory device, receiving first read data and first distribution information corresponding to the read command from the non-volatile memory device, determining whether an error of the first read data is uncorrectable, and updating offset information of a history table in the storage controller based on the first distribution information, in response to determining that the error of the first read data is correctable.

公开(公告)号：US20240177764A1

公开(公告)日：2024-05-30

申请号：US18223783

申请日：2023-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chang Jeon ,  Woohyun Kang ,  Seungkyung Ro ,  Sangkwon Moon ,  Heewon Lee

IPC: G11C11/408 ,  G06F3/06

CPC classification number: G11C11/4085 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4087

Abstract: Disclosed is a nonvolatile memory device which include a memory cell array including a plurality of memory cells connected to a plurality of word lines, an address decoder that controls a selected word line among the plurality of word lines based on an address received from an external device including a first temperature sensor, a second temperature sensor that measures a read temperature of first memory cells connected to the selected word line from among the plurality of memory cells, and a temperature compensation circuit that calculates a read level offset based on the read temperature and a program temperature of the first memory cells measured by the first temperature sensor and generates a compensation read voltage based on the read level offset. The address decoder is further configured to provide the compensation read voltage to the selected word line.

公开(公告)号：US09543026B2

公开(公告)日：2017-01-10

申请号：US14865275

申请日：2015-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Song ,  Minsu Kim ,  Il-Han Park ,  Su Chang Jeon

IPC: G11C7/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2207/005

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

Abstract translation: 提供了一种非易失性存储器件的操作方法。 非易失性存储器件分别包括第一和第二页缓冲器以及与其相连的第一和第二位线。 第一页缓冲器的第一和第二锁存节点被充电以具有根据存储在第一页缓冲器的第一锁存器中的数据具有第一电平的电压。 在第一锁存节点的充电开始之后，第二页缓冲器的感测节点被预充电。 感测节点连接到第二位线。 存储在第一锁存器中的数据在第二页缓冲器的感测节点的预充电期间被转储到第一页缓冲器的第二锁存器中。

公开(公告)号：US20160093388A1

公开(公告)日：2016-03-31

申请号：US14865275

申请日：2015-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO SONG ,  Minsu Kim ,  Il-Han Park ,  Su Chang Jeon

IPC: G11C16/24 ,  G11C16/32 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2207/005

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

Abstract translation: 提供了一种非易失性存储器件的操作方法。 非易失性存储器件分别包括第一和第二页缓冲器以及与其相连的第一和第二位线。 第一页缓冲器的第一和第二锁存节点被充电以具有根据存储在第一页缓冲器的第一锁存器中的数据具有第一电平的电压。 在第一锁存节点的充电开始之后，第二页缓冲器的感测节点被预充电。 感测节点连接到第二位线。 存储在第一锁存器中的数据在第二页缓冲器的感测节点的预充电期间被转储到第一页缓冲器的第二锁存器中。