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    Semiconductor memory device and memory system including the same
    11.
    发明授权
    Semiconductor memory device and memory system including the same 有权

    公开(公告)号：US11947810B2

    公开(公告)日：2024-04-02

    申请号：US17743137

    申请日：2022-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungrae Kim ,  Hyeran Kim ,  Myungkyu Lee ,  Chisung Oh ,  Kijun Lee ,  Sunghye Cho ,  Sanguhn Cha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

    Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

    Semiconductor memory devices and memory systems
    12.
    发明授权
    Semiconductor memory devices and memory systems 有权

    公开(公告)号：US11860734B2

    公开(公告)日：2024-01-02

    申请号：US17736154

    申请日：2022-05-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sunghye Cho ,  Yeonggeol Song ,  Kijun Lee ,  Myungkyu Lee

    IPC: G11C29/00 ,  G06F11/10 ,  H03M13/11 ,  G06F11/07

    CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/1048 ,  H03M13/1108

    Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, and a control logic circuit. The on-die ECC engine, based on an ECC, in a write operation, performs an ECC encoding on main data to generate first parity data, selectively replaces a portion of the first parity data with a poison flag to generate second parity data based on a poison mode signal, provides the main data to a normal cell region in a target page of the memory cell array, and provides the first parity data to a parity cell region in the target page or provides the poison flag and the second parity data to the parity cell region. The control logic circuit controls the on-die ECC engine and generates the poison mode signal, based on a command and an address from a memory controller.

    Semiconductor memory devices and methods of operating semiconductor memory devices
    13.
    发明授权
    Semiconductor memory devices and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11829614B2

    公开(公告)日：2023-11-28

    申请号：US17842981

    申请日：2022-06-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho

    IPC: G06F3/06 ,  G06F11/10

    CPC classification number: G06F3/0626 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068

    Abstract: A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME
    14.
    发明公开
    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME 审中-公开

    公开(公告)号：US20230376414A1

    公开(公告)日：2023-11-23

    申请号：US18318906

    申请日：2023-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

    IPC: G06F12/06

    CPC classification number: G06F12/06

    Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    15.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20230037996A1

    公开(公告)日：2023-02-09

    申请号：US17718422

    申请日：2022-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Myungkyu Lee ,  Kijun Lee ,  Sunghye Cho

    IPC: H03M13/11 ,  H03M13/15 ,  G11C15/04 ,  G11C17/16

    Abstract: An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.

    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME
    17.
    发明申请
    MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME 有权

    公开(公告)号：US20250165395A1

    公开(公告)日：2025-05-22

    申请号：US19028378

    申请日：2025-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

    IPC: G06F12/06 ,  G06F11/10

    Abstract: A memory controller generates a command address signal (CAS), and includes a first bit signal generator (BSG) configured to generate a data signal (DS) as a plurality of data bits, a second BSG configured to generate a command address bus inversion bit (CABIB) having a logic level that is a function of a number of data bits within the DS having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the DS and the CABIB having a high level is an even number. The CABIB is set to a high logic level when “n”, which is a number of bits included in the CAS, is a positive integer greater than one, and a number of data bits within the DS having a low level is greater than or equal to (n/2)−1.

    Error correction circuit, memory system, and error correction method
    18.
    发明授权
    Error correction circuit, memory system, and error correction method 有权

    公开(公告)号：US12212339B2

    公开(公告)日：2025-01-28

    申请号：US17984430

    申请日：2022-11-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myungkyu Lee ,  Kijun Lee ,  Sunghye Cho ,  Sungrae Kim

    IPC: H03M13/15 ,  H03M13/00

    Abstract: An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

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