公开(公告)号：US12051754B2

公开(公告)日：2024-07-30

申请号：US17862909

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Junbeom Park ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

公开(公告)号：US20220352388A1

公开(公告)日：2022-11-03

申请号：US17862909

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUJIN JUNG ,  Junbeom Park ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

公开(公告)号：US10903108B2

公开(公告)日：2021-01-26

申请号：US15869718

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon Kim ,  Seung Hun Lee ,  Yang Xu ,  Jeongho Yoo ,  Jongryeol Yoo ,  Youngdae Cho

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.

公开(公告)号：US20200219976A1

公开(公告)日：2020-07-09

申请号：US16666958

申请日：2019-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Sunguk Jang ,  Pankwi Park ,  Sangmoon Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).

公开(公告)号：US11862733B2

公开(公告)日：2024-01-02

申请号：US17480457

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Kihwan Kim ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7854

Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

公开(公告)号：US11616144B2

公开(公告)日：2023-03-28

申请号：US16412796

申请日：2019-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunguk Jang ,  Sujin Jung ,  Jinyeong Joe ,  Jeongho Yoo ,  Seung Hun Lee ,  Jongryeol Yoo

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.

公开(公告)号：US11195954B2

公开(公告)日：2021-12-07

申请号：US16732864

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

公开(公告)号：US11177346B2

公开(公告)日：2021-11-16

申请号：US16666958

申请日：2019-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Sunguk Jang ,  Pankwi Park ,  Sangmoon Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).

公开(公告)号：US20200381563A1

公开(公告)日：2020-12-03

申请号：US16734537

申请日：2020-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Kihwan Kim ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.

公开(公告)号：US20200381562A1

公开(公告)日：2020-12-03

申请号：US16715431

申请日：2019-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  Junbeom Park ,  Kihwan Kim ,  Sunguk Jang ,  Youngdae Cho

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.