公开(公告)号：US20180108540A1

公开(公告)日：2018-04-19

申请号：US15636849

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Phee ,  Ho-Jin Lee ,  Taeseong Kim ,  Kwangjin Moon ,  Jin Ho An ,  Naein Lee

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L23/64 ,  H01L23/00 ,  H05K3/40 ,  H05K1/16

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/544 ,  H01L23/642 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/37001 ,  H05K1/162 ,  H05K3/4038 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening.

公开(公告)号：US20140008815A1

公开(公告)日：2014-01-09

申请号：US13911569

申请日：2013-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeun-Sang Park ,  Byung-Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Kwangjin Moon ,  Sukchul Bang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.

Abstract translation: 公开了半导体器件。 半导体器件可以包括具有彼此相对的第一表面和第二表面的半导体衬底和形成在第二表面的一部分处的衬垫沟槽，穿透半导体衬底并从衬底的底表面突出的通孔 沟。 掩埋焊盘可以设置在焊盘沟槽中并且可以围绕通孔。

公开(公告)号：US12046538B2

公开(公告)日：2024-07-23

申请号：US18354068

申请日：2023-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L27/088 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US11955408B2

公开(公告)日：2024-04-09

申请号：US17036145

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sohye Cho ,  Pilkyu Kang ,  Kwangjin Moon ,  Taeseong Kim

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/50 ,  H01L23/528 ,  H10B10/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5286 ,  H10B10/12 ,  H01L23/50

Abstract: An integrated circuit semiconductor device includes a substrate including a first surface and a second surface opposite the first surface, a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate, a through silicon via (TSV) landing part in the trench, the TSV landing part having a first portion spaced apart from the first surface of the substrate, and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion, a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part, and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

公开(公告)号：US20230230995A1

公开(公告)日：2023-07-20

申请号：US18191218

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan HONG ,  Taeseong Kim

IPC: H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/1469 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/80 ,  H01L23/481 ,  H01L2224/80894 ,  H01L2224/08146

Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

公开(公告)号：US20210005533A1

公开(公告)日：2021-01-07

申请号：US16750579

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoukyung Cho ,  Daesuk Lee ,  Jinnam Kim ,  Taeseong Kim ,  Kwangjin Moon ,  Hakseung Lee

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

公开(公告)号：US11664316B2

公开(公告)日：2023-05-30

申请号：US16849085

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Hyoukyung Cho ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/5385 ,  H01L2224/08146

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

公开(公告)号：US11295981B2

公开(公告)日：2022-04-05

申请号：US16734456

申请日：2020-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L21/02 ,  H01L21/768

Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

公开(公告)号：US10734430B2

公开(公告)日：2020-08-04

申请号：US16233900

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Taeseong Kim

IPC: H01L23/48 ,  H01L27/146 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

公开(公告)号：US08836142B2

公开(公告)日：2014-09-16

申请号：US13911569

申请日：2013-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeun-Sang Park ,  Byung-Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Kwangjin Moon ,  Sukchul Bang

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.

Abstract translation: 公开了半导体器件。 半导体器件可以包括具有彼此相对的第一表面和第二表面的半导体衬底和形成在第二表面的一部分处的衬垫沟槽，穿透半导体衬底并从衬底的底表面突出的通孔 沟。 掩埋焊盘可以设置在焊盘沟槽中并且可以围绕通孔。