公开(公告)号：US11277272B2

公开(公告)日：2022-03-15

申请号：US16567751

申请日：2019-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunhyeok Choi ,  Yongki Lee ,  Yongsoo Kim ,  Jieun Park ,  Bohdan Karpinskyy

IPC: H04L9/00 ,  H04L9/32 ,  H04L9/08

Abstract: Systems and methods are described based on an integrated circuit that performs a challenge-response physically unclonable function (PUF). The PUF is used for challenge-response authentication. The integrated circuit includes a PUP block configured to output an n-bit internal response corresponding to a challenge that requests a response where n is an integer greater than 1 and a response generator configured to calculate a Hamming weight of the internal response and output the response by comparing the Hamming weight with at least one reference.

公开(公告)号：US12164376B2

公开(公告)日：2024-12-10

申请号：US18148061

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Taewook Park ,  Jisu Kang ,  Yongki Lee

IPC: G06F11/10 ,  G06F11/07

Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.

公开(公告)号：US11996857B2

公开(公告)日：2024-05-28

申请号：US17827135

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungno Lee ,  Heechang Hwang ,  Yongki Lee ,  Kyoungjun Moon ,  Hyochul Shin ,  Michael Choi

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: An analog-to-digital conversion circuit includes analog-to-digital converters (ADCs) including a target analog-to-digital converter (ADC) providing second data samples, a first adjacent ADC providing first data samples, and a second adjacent ADC providing third data samples. The ADCs perform an analog-to-digital conversion using a time-interleaving approach in response to clock signals having different phases and including a reference clock signal. A timing calibration circuit includes a relative time skew generator generating a relative time skew and an absolute time skew generator generate an absolute time skew. A clock generator adjusts at least one phase of the clock signals based on the absolute time skew.

公开(公告)号：US11698410B2

公开(公告)日：2023-07-11

申请号：US17471763

申请日：2021-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Hyochul Shin ,  Jinwoo Park ,  Sungno Lee ,  Younghyo Park ,  Yongki Lee ,  Heejune Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/28 ,  H03K5/24 ,  H03M1/12

CPC classification number: G01R31/2884 ,  H03K5/24 ,  H03M1/124

Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

公开(公告)号：US20230153069A1

公开(公告)日：2023-05-18

申请号：US17944486

申请日：2022-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieun Park ,  Yongki Lee ,  Sumin Noh ,  Yunhyeok Choi ,  Bohdan Karpinskyy

IPC: G06F7/58

CPC classification number: G06F7/58

Abstract: A random number generator according to example embodiments includes an initial random number generator configured to generate an initial random number, a self-timed ring (STR) oscillator configured to receive the initial random number, the STR oscillator having a plurality of ring stages generating, in response to a clock, either a bubble that does not change an output state of a previous clock or a token changing the output state of the previous clock, a duty corrector configured to adjust a duty of each of output values of the ring stages, and a sampling circuit configured to sample a random number using a logic operation from the duty-corrected output values.

公开(公告)号：US11651071B2

公开(公告)日：2023-05-16

申请号：US17003313

申请日：2020-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bohdan Karpinskyy ,  Mijung Noh ,  Jieun Park ,  Yongki Lee ,  Juyeon Lee

IPC: G06F21/55 ,  G06F7/58 ,  H03K3/84 ,  H03K19/20 ,  H03K19/21

CPC classification number: G06F21/552 ,  G06F7/582 ,  G06F7/588 ,  H03K3/84 ,  G06F2221/034 ,  H03K19/20 ,  H03K19/21

Abstract: An apparatus includes an integrated circuit and a plurality of conducting wires disposed on the integrated circuit. The integrated circuit includes: (i) a signal generation circuit, which is configured to generate random signal and selection signal based on random or pseudo-random numbers, (ii) a transmitting circuit configured to select at least one from among the plurality of conducting wires based on the selection signal and to output the random signal through the at least one conducting wire, and (iii) a receiving circuit configured to detect an invasive attack on the integrated circuit based on signal received through the at least one conducting wire.

公开(公告)号：US11516026B2

公开(公告)日：2022-11-29

申请号：US17014418

申请日：2020-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungmoon Ahn ,  Yongsoo Kim ,  Yongki Lee ,  Yunhyeok Choi ,  Bohdan Karpinskyy

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/08 ,  G06F21/64

Abstract: A security device generates a key based on a physically unclonable function (PUF). The security device includes a physically unclonable function (PUF) block, an integrity detector, and a post processor. The PUF block outputs a plurality of first random signals and a plurality of corresponding first inverted random signals each having a logic level opposite to that of each of the plurality of corresponding first random signals. The integrity detector determines data integrity of the plurality of first random signals by using the plurality of first random signals and the plurality of corresponding first inverted random signals. The post processor generates a first row key that includes validity signals satisfying the data integrity.