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    SEMICONDUCTOR MEMORY DEVICE
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190287977A1

    公开(公告)日：2019-09-19

    申请号：US16419947

    申请日：2019-05-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

    IPC: H01L27/108

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    METHODS OF FABRICATING SEMICONDUCTOR MEMORY DEVICES
    12.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20180301459A1

    公开(公告)日：2018-10-18

    申请号：US15952350

    申请日：2018-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eunjung KIM ,  Daeik KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Semyeong JANG ,  Yoosang HWANG

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02 ,  B08B7/00

    Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME
    13.
    发明公开
    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240114676A1

    公开(公告)日：2024-04-04

    申请号：US18525187

    申请日：2023-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin PARK ,  Taehoon KIM ,  Kyujin KIM ,  Chulkwon PARK ,  Sunghee HAN ,  Yoosang HWANG

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE ELECTRODE INCLUDING STEP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    14.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE ELECTRODE INCLUDING STEP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220246621A1

    公开(公告)日：2022-08-04

    申请号：US17725806

    申请日：2022-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehwan CHO ,  Junghwan OH ,  Sangho LEE ,  Junwon LEE ,  Jinwoo BAE ,  Sunghee HAN ,  Yoosang HWANG

    IPC: H01L27/108

    Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

    SEMICONDUCTOR MEMORY DEVICE
    15.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210043629A1

    公开(公告)日：2021-02-11

    申请号：US16880230

    申请日：2020-05-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung KIM ,  Taehyun AN ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

    IPC: H01L27/108 ,  G11C5/06

    Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

    SEMICONDUCTOR MEMORY DEVICES
    17.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190103407A1

    公开(公告)日：2019-04-04

    申请号：US16038052

    申请日：2018-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/0688 ,  H01L27/1085 ,  H01L28/86

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

    SEMICONDUCTOR DEVICES HAVING AIR SPACERS AND METHODS OF MANUFACTURING THE SAME
    19.
    发明申请
    SEMICONDUCTOR DEVICES HAVING AIR SPACERS AND METHODS OF MANUFACTURING THE SAME 有权
    具有空气间隔的半导体器件及其制造方法

    公开(公告)号：US20170062347A1

    公开(公告)日：2017-03-02

    申请号：US15095327

    申请日：2016-04-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung-Eun KIM ,  Yongkwan KIM ,  Semyeong JANG ,  Jaehyoung CHOI ,  Yoosang HWANG ,  Bong-Soo KIM

    IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108

    CPC classification number: H01L23/4821 ,  H01L21/76264 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

    Abstract: A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

    Abstract translation: 半导体器件包括在衬底上彼此间隔开的第一和第二位线结构，部分地填充在第一和第二位线结构之间的通孔插头，与通孔插头的上表面接触的通孔焊盘和上部 第一位线结构的侧壁，通孔焊盘与第二位线结构的上部间隔开，填充有通孔插塞和第一位线结构之间的空气的第一腔体和填充有空气的第二腔体， 所述通孔插头和所述第二位线结构。具有位于所述第一位线结构的上侧壁上的第一部分的间隙封盖间隔件以及覆盖所述第一空气间隔件的第二部分。 第一部分的水平宽度小于第二部分的水平宽度。

    SEMICONDUCTOR MEMORY DEVICE
    20.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230044856A1

    公开(公告)日：2023-02-09

    申请号：US17873242

    申请日：2022-07-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejin PARK ,  Kiseok LEE ,  Hui-Jung KIM ,  Yoosang HWANG

    IPC: H01L29/423 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02 ,  G11C5/06

    Abstract: A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.

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