公开(公告)号：US10978431B2

公开(公告)日：2021-04-13

申请号：US16287249

申请日：2019-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongbo Shim ,  Ji Hwang Kim ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.

公开(公告)号：US10748953B2

公开(公告)日：2020-08-18

申请号：US16803041

申请日：2020-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghoe Cho ,  Jongbo Shim ,  Seunghoon Yeon ,  Won Il Lee

IPC: H01L21/00 ,  H01L27/146

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a top surface, on which has been formed a color filter and a micro-lens, and a bottom surface opposite to the top surface, forming a redistribution line on the bottom surface of the semiconductor substrate, and forming on the bottom surface of the semiconductor substrate a passivation layer covering the redistribution line. After the redistribution line and passivation layer are formed, an oxide layer between the redistribution line and the passivation is formed at a temperature that avoids thermal damage to the color filter and the micro-lens.

公开(公告)号：US10361170B2

公开(公告)日：2019-07-23

申请号：US15837187

申请日：2017-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun Pyo ,  Jongbo Shim ,  Ji Hwang Kim ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

公开(公告)号：US20250062172A1

公开(公告)日：2025-02-20

申请号：US18782267

申请日：2024-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H10B80/00

Abstract: A semiconductor package includes a package substrate, a first semiconductor device on the package substrate, a second semiconductor device on the package substrate and spaced laterally from the first semiconductor device, and a package encapsulant including a first encapsulant and a second encapsulant. The first encapsulant is on the package substrate, is in contact with side surfaces of the first semiconductor device, and encloses the side surfaces of the first semiconductor device. The second encapsulant is on the package substrate and laterally spaced apart from some side surfaces of the second semiconductor device, wherein the first encapsulant and the second encapsulant are integrally provided, and some side surfaces of the package encapsulant are coplanar with an outer edge of the package substrate.

公开(公告)号：US12033924B2

公开(公告)日：2024-07-09

申请号：US17542828

申请日：2021-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Hwanpil Park ,  Jongbo Shim

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L23/49811 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, an interposer, a semiconductor chip between the package substrate and the interposer, a plurality of conductive connectors between the package substrate and the interposer, and a capacitor stack structure between the package substrate and the interposer, he capacitor stack structure including a first capacitor connected to the package substrate, and a second capacitor connected to the interposer.

公开(公告)号：US12021036B2

公开(公告)日：2024-06-25

申请号：US17986169

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongbo Shim ,  Jihwang Kim ,  Choongbin Yim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

公开(公告)号：US11854989B2

公开(公告)日：2023-12-26

申请号：US17167789

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongho Kim ,  Jongbo Shim ,  Hwan Pil Park ,  Choongbin Yim ,  Jungwoo Kim

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

公开(公告)号：US11804477B2

公开(公告)日：2023-10-31

申请号：US17371834

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16155 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L2924/186

Abstract: A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

公开(公告)号：US11798889B2

公开(公告)日：2023-10-24

申请号：US17835768

申请日：2022-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jongbo Shim ,  Kyoungsei Choi

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14

CPC classification number: H01L23/5384 ,  H01L23/14 ,  H01L23/31 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

公开(公告)号：US20220181309A1

公开(公告)日：2022-06-09

申请号：US17371834

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyun Lee ,  Jihwang Kim ,  Jongbo Shim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.