公开(公告)号：US20180083099A1

公开(公告)日：2018-03-22

申请号：US15628675

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGMIN BAEK ,  VIETHA NGUYEN ,  WOOKYUNG YOU ,  Sangshin JANG ,  BYUNGHEE KIM ,  Kyu-Hee HAN

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/768

Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.

公开(公告)号：US20240112949A1

公开(公告)日：2024-04-04

申请号：US18537896

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L23/481 ,  H01L21/76832

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20230395667A1

公开(公告)日：2023-12-07

申请号：US18117837

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyu-Hee HAN ,  Bong Kwan Baek ,  Jung Hwan Chun ,  Koung Min RYN ,  Jong Min Baek ,  Jung Hoo Shin ,  Jun Hyuk Lim ,  Sang Shin Jang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/41733 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/41775

Abstract: Provided is a semiconductor device including an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction. A lower surface of the contact liner structure is higher than an upper surface of the source/drain pattern.

公开(公告)号：US20210020497A1

公开(公告)日：2021-01-21

申请号：US16798789

申请日：2020-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20190157214A1

公开(公告)日：2019-05-23

申请号：US16027484

申请日：2018-07-05

Applicant: Samsung Electronics Co. Ltd.

Inventor： Jun Kwan KIM ,  Sanghoon AHN ,  Kyu-Hee HAN ,  JaeWha PARK ,  Heesook PARK

IPC: H01L23/532 ,  H01L23/522

Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

公开(公告)号：US20190139813A1

公开(公告)日：2019-05-09

申请号：US16242483

申请日：2019-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Shin JANG ,  Woo-Kyung YOU ,  Kyu-Hee HAN ,  Jong-Min BAEK ,  Viet Ha NGUYEN ,  Byung-Hee KIM

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.

公开(公告)号：US20170092480A1

公开(公告)日：2017-03-30

申请号：US15000001

申请日：2016-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Sun YI ,  Ki-Chul KIM ,  Jong-Cheol LEE ,  Kyu-Hee HAN ,  Jae-Chul SHIN ,  Min-Hwa JUNG ,  Yu-Ho Won ,  Seung-Han LEE ,  Jin-Pil HEO

IPC: H01L21/02 ,  C23C16/458 ,  C23C16/455

CPC classification number: H01L21/0262 ,  C23C16/4412 ,  C23C16/45551 ,  C23C16/45574 ,  C23C16/4584

Abstract: Provided are gas injection apparatuses, thin-film deposition equipment, and methods for manufacturing a semiconductor device. The gas injection apparatus includes: a base plate; a first gas separation region on the base plate; first and second source gas supplying regions disposed on the base plate to either side of the first gas separation region, respectively, and configured to supply a source gas; and a first reaction gas supplying region disposed at a position on the base plate other than between the first gas separation region and the first source gas supplying region and between the first gas separation region and the second source gas supplying region, and configured to supply a reaction gas, wherein the first source gas supplying region and the second source gas supplying region protrude from the base plate, wherein each of the first source gas supplying region and the second source gas supplying region has a fan-shaped upper face, and wherein the first gas separation region is defined by a side wall of the first source gas supplying region and a side wall of the second source gas supplying region, the side walls facing each other and extending in radial directions.

公开(公告)号：US20140225251A1

公开(公告)日：2014-08-14

申请号：US14134043

申请日：2013-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Hee LEE ,  Jongmin BAEK ,  Kyu-Hee HAN ,  Gilheyun CHOI ,  Jongwon HONG

IPC: H01L23/28 ,  H01L23/48

CPC classification number: H01L23/4821 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/28 ,  H01L23/48 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/0001

Abstract: Semiconductor devices, and methods of fabricating the same, include first conductive lines on a substrate, and a first molding layer covering the first conductive lines. The first conductive lines have air gaps between adjacent first conductive lines. Sidewalls of the first conductive lines and a bottom surface of the first molding layer collectively define a first gap region of each of the air gaps. The sidewalls of the first conductive lines and a top surface of the first molding layer collectively define a second air gap region of each of the air gaps.

Abstract translation: 半导体器件及其制造方法包括在基板上的第一导线和覆盖第一导线的第一成型层。 第一导线在相邻的第一导线之间具有气隙。 第一导电线的侧壁和第一模制层的底表面共同限定每个气隙的第一间隙区域。 第一导电线的侧壁和第一模制层的顶表面共同限定每个气隙的第二气隙区域。