公开(公告)号：US20140226406A1

公开(公告)日：2014-08-14

申请号：US13940504

申请日：2013-07-12

申请人： SanDisk Technologies Inc.

发明人： Yingda Dong ,  Cynthia Hsu ,  Man L. Mui ,  Manabu Sakai ,  Toru Miwa ,  Masaaki Higashitani

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3468 ,  G11C16/349

摘要： In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

摘要翻译： 在3D堆叠非易失性存储器件的编程操作中，首先将所选字线层上的初始存储器单元集合（其涉及少于所选字线层上的所有存储器单元）作为测试用例来确定最佳值 用于编程所选字线层上的剩余存储单元的条件。 例如，确定了将初始存储器单元组编程为初始量所需的多个程序验证迭代或循环。 然后，该循环计数例如在存储单元的初始组内，剩余存储单元内，剩余字线层或数据寄存器中的存储器单元内存储，并且初始存储器单元组的编程继续 完成 随后，检索循环计数并用于确定用于编程剩余存储单元的最佳启动程序电压。

公开(公告)号：US20140211568A1

公开(公告)日：2014-07-31

申请号：US13754852

申请日：2013-01-30

申请人： SANDISK TECHNOLOGIES INC.

发明人： Man L. Mui ,  Teruhiko Kamei ,  Yingda Dong ,  Ken Oowada ,  Yosuke Kato ,  Fumitoshi Ito ,  Seungpil Lee

IPC分类号： G11C16/28

CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

摘要翻译： 在选择要被感测的非易失性存储元件时，系统获得关于这些非易失性存储元件的位置的信息，至少部分地基于该信息来确定感测参数，对电荷存储装置进行预充电，并且在保持 这些存储单元的位线的电压电平处于恒定值，将参考信号施加到这些非易失性存储元件一定的持续时间，然后确定在一定持续时间内由这些非易失性存储元件 非易失存储元件超过预定值。

公开(公告)号：US09013928B1

公开(公告)日：2015-04-21

申请号：US14561841

申请日：2014-12-05

申请人： SanDisk Technologies Inc.

发明人： Deepanshu Dutta ,  Ken Oowada ,  Masaaki Higashitani ,  Man L. Mui

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C7/12 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3459

摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.

公开(公告)号：US20150043278A1

公开(公告)日：2015-02-12

申请号：US14524153

申请日：2014-10-27

申请人： SanDisk Technologies Inc.

发明人： Xiying Costa ,  Alex Mak ,  Johann Alsmeier ,  Man L. Mui

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3445 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11582

摘要： An erase operation for a 3D stacked memory device assigns storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

摘要翻译： 3D堆叠存储器件的擦除操作根据预期的擦除速度将存储元件分配给组。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

公开(公告)号：US08953386B2

公开(公告)日：2015-02-10

申请号：US13660203

申请日：2012-10-25

申请人： SanDisk Technologies Inc.

发明人： Deepanshu Dutta ,  Ken Oowada ,  Masaaki Higashitani ,  Man L. Mui

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C7/12 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3459

摘要： A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level.

摘要翻译： 用于一组非易失性存储元件的程序操作。 维持以慢编程模式施加到单个存储元件的多个编程脉冲的计数，并且基于计数调整相关联的位线电压。 可以使用不同的位线电压，具有公共的步长或不同的步长。 结果，缓慢编程模式下的存储元件的阈值电压的变化可以使每个编程脉冲均匀，从而提高编程精度。 在缓慢编程模式下，锁存器保持相关存储元件所经历的程序脉冲计数。 当其阈值电压低于较低验证电平时，存储元件处于快速编程模式，而当其阈值电压处于较低验证电平和较高验证电平之间时，存储元件处于慢速编程模式。

公开(公告)号：US08824211B1

公开(公告)日：2014-09-02

申请号：US13767708

申请日：2013-02-14

申请人： SanDisk Technologies Inc.

发明人： Xiying Costa ,  Alex Mak ,  Johann Alsmeier ,  Man L. Mui

IPC分类号： G11C11/34 ,  G11C16/14

CPC分类号： G11C16/3445 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11582

摘要： An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.

摘要翻译： 根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。 然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。 在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。 可以将所有组一起设置为擦除或禁止状态。 在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

公开(公告)号：US20140043916A1

公开(公告)日：2014-02-13

申请号：US13960360

申请日：2013-08-06

申请人： SanDisk Technologies Inc.

发明人： Xiying Costa ,  Seung Yu ,  Roy E. Scheuerlein ,  Haibo Li ,  Man L. Mui

IPC分类号： G11C16/14 ,  G11C16/24

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/24 ,  G11C16/3445 ,  H01L27/11551 ,  H01L27/11582 ,  H01L29/7926

摘要： An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.

摘要翻译： 3D堆叠存储器件的擦除操作基于存储元件的位置来调整每个存储元件的擦除周期的开始时间和/或擦除周期的持续时间。 电压施加到NAND串的一个或两个驱动端，以将通道预充电到足以在选择栅极晶体管处产生栅极引起的漏极泄漏的电平。 通过基于存储元件与驱动端的距离的定时，降低控制栅极电压，以在擦除期间促进空穴穿入电荷捕获层。 降低的控制栅极电压导致通道对控制栅极电压足够高以鼓励隧穿。 当从驱动端的距离较大时，擦除周期的持续时间也增加。 结果，可以实现窄的擦除分布。

公开(公告)号：US20150221348A1

公开(公告)日：2015-08-06

申请号：US14616289

申请日：2015-02-06

申请人： SanDisk Technologies Inc.

发明人： Tai-Yuan Tseng ,  Yenlung Li ,  Cynthia Hsu ,  Kwang Ho Kim ,  Man L. Mui

IPC分类号： G11C7/06 ,  G06F3/06 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459

摘要： A non-volatile memory includes an efficient data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.

摘要翻译： 非易失性存储器包括用于使用至少三个编程级别对位线进行编程的有效数据锁存结构。 读出放大器包括用于控制相应位线的电压的第一数据锁存器和具有扫描电路的第二静态数据锁存器，用于对程序数据执行逻辑运算并感测结果。 读出放大器利用程序数据扫描低校验感应结果，以产生简化的编程数据。 在感测所有状态之后，将减少的编程数据从第一数据锁存器传送出去，并且扫描程序数据以产生存储在第一数据锁存器中的程序使能/禁止数据。 在将位线设置为程序禁止或程序使能电平之后，减小的编程数据被传送回第一数据锁存器。 然后，用于减少编程的位线被调整到降低的编程电平。

公开(公告)号：US20150170748A1

公开(公告)日：2015-06-18

申请号：US14631080

申请日：2015-02-25

申请人： SanDisk Technologies Inc.

发明人： Xiying Costa ,  Haibo Li ,  Masaaki Higashitani ,  Man L. Mui

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3445 ,  G11C16/3472 ,  H01L27/1157 ,  H01L27/11582

摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

摘要翻译： 用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。 当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。 在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以从更高的栅极引起的漏极泄漏（GIDL）电流中受益，以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

公开(公告)号：USRE45567E1

公开(公告)日：2015-06-16

申请号：US14177756

申请日：2014-02-11

申请人： SANDISK TECHNOLOGIES INC.

发明人： Tien-chien Kuo ,  Man L. Mui

IPC分类号： G11C11/34 ,  G11C5/14 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C5/14 ,  G11C7/10 ,  G11C16/06

摘要： A power supply and monitoring apparatus such as in a non-volatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing operation, such as a read or verify operation, a discharge period is set in which a sense node of each sense module discharges into the associated bit line and string of non-volatile storage elements, when the string of non-volatile storage elements, is conductive. This discharge sinks current from the power supply, causing a perturbation. By sampling the power supply, a steady state condition can be detected from a rate of change. The steady state condition signals that the discharge period can be concluded and data can be latched from the sense node. The discharge period automatically adapts to different memory devices and environmental conditions.

摘要翻译： 诸如在非易失性存储器系统中的电源和监视装置。 电源电路为大量的感测模块提供电力，每个感测模块与位线和一串非易失性存储元件相关联。 在诸如读取或验证操作的感测操作期间，设置放电周期，其中每个感测模块的感测节点放电到相关联的位线和非易失性存储元件串中，当非易失性存储器串 元件，是导电的。 该放电从电源吸收电流，引起扰动。 通过对电源进行采样，可以从变化率检测稳定状态。 稳态条件指示放电周期可以结束，数据可以从感测节点锁存。 放电周期自动适应不同的存储器件和环境条件。