公开(公告)号：US5107459A

公开(公告)日：1992-04-21

申请号：US513315

申请日：1990-04-20

申请人： Christopher M. Chu ,  Sang H. Dhong ,  Wei Hwang ,  Nicky C-C. Lu

发明人： Christopher M. Chu ,  Sang H. Dhong ,  Wei Hwang ,  Nicky C-C. Lu

IPC分类号： H01L27/10 ,  G11C11/401 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10841 ,  G11C11/4097

摘要： A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.

公开(公告)号：US4910709A

公开(公告)日：1990-03-20

申请号：US230410

申请日：1988-08-10

申请人： Sang H. Dhong ,  Nicky C. Lu ,  Walter H. Henkels

发明人： Sang H. Dhong ,  Nicky C. Lu ,  Walter H. Henkels

IPC分类号： G11C11/405 ,  G11C11/404 ,  G11C11/409 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/092 ,  H01L27/108

CPC分类号： G11C11/404 ,  H01L27/0688 ,  H01L27/108

摘要： A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

公开(公告)号：US4894697A

公开(公告)日：1990-01-16

申请号：US264418

申请日：1988-10-31

申请人： Daeje Chin ,  Sang H. Dhong

发明人： Daeje Chin ,  Sang H. Dhong

IPC分类号： H01L27/10 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10864 ,  H01L21/3065 ,  H01L27/10841

摘要： This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells. A pair of gates are disposed in insulating conduits which run perpendicular to the rows of memory cells. Each gate in a conduit is disposed in insulating spaced relationship with a memory cell channel region which, in response to signals on the gate turns on a column of channel regions so as to permit the entry of charge into a selected storage region when a bitline associated with a particular cell is energized. The resulting array shows rows of pairs of memory cells wherein each cell of a pair is spaced from the other by a portion of the substrate acting as a counterelectrode and each of the pairs of memory cells is similarly separated from an adjacent pair by regions of conductive material acting as a counterelectrode.

公开(公告)号：US08618592B2

公开(公告)日：2013-12-31

申请号：US13098193

申请日：2011-04-29

申请人： Hyun-Jin Cho ,  Sang H. Dhong ,  Jung-Suk Goo ,  Gurupada Mandal

发明人： Hyun-Jin Cho ,  Sang H. Dhong ,  Jung-Suk Goo ,  Gurupada Mandal

IPC分类号： H01L21/00

CPC分类号： H01L27/10802 ,  H01L27/108 ,  H01L27/1082 ,  H01L27/1087 ,  H01L29/7841

摘要： A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.

摘要翻译： 提供一种包括沟槽电容器和存取晶体管的半导体存储单元。 存取晶体管包括源区域，漏极区域，覆盖沟槽电容器的栅极结构以及将漏极区域耦合到源极区域的有源体区域。 有源体区域直接接触沟槽电容器。

公开(公告)号：US07977172B2

公开(公告)日：2011-07-12

申请号：US12330282

申请日：2008-12-08

申请人： Hyun-Jin Cho ,  Sang H. Dhong ,  Jung-Suk Goo ,  Gurupada Mandal

发明人： Hyun-Jin Cho ,  Sang H. Dhong ,  Jung-Suk Goo ,  Gurupada Mandal

IPC分类号： H01L21/84

CPC分类号： H01L27/10802 ,  H01L27/108 ,  H01L27/1082 ,  H01L27/1087 ,  H01L29/7841

摘要： A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.

摘要翻译： 提供一种制造存储单元的方法。 在包括半导体层的半导体结构中形成沟槽，并且在沟槽中形成沟槽电容器。 将导电性确定杂质注入到半导体结构中以在直接耦合到沟槽电容器的半导体层中形成阱区。 形成覆盖阱区域的一部分的栅极结构。 然后将确定电导的离子注入阱区的其它部分以形成源区和漏区，并且在源区和漏区之间限定有源体区。 有源体区域直接接触沟槽电容器。

公开(公告)号：US07610531B2

公开(公告)日：2009-10-27

申请号：US11531287

申请日：2006-09-13

申请人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

发明人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318575

摘要： Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

摘要翻译： 提供了修改测试模式以控制电源噪声的机制。 修改测试图形波形的测试序列中的状态序列的一部分被修改，以便实现近似标称电路电压的电路电压，例如片上电压，例如通过施加其它部分产生的电压 的相同或不同测试序列中的状态序列。 例如，保持状态周期或移位扫描状态周期可以在测试模式波形中的测试状态周期之前被插入或移除。 插入/移除将测试状态周期的发生移动到测试图形波形内，以便调整测试状态周期的电压响应，使得它们更接近于额定电压响应。 以这种方式，可以消除由于电压源中的噪声引起的错误故障。

公开(公告)号：US20080168318A1

公开(公告)日：2008-07-10

申请号：US11621766

申请日：2007-01-10

申请人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

发明人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

IPC分类号： G01R31/30 ,  G06F11/00

CPC分类号： G01R31/3004 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

公开(公告)号：US20080021692A1

公开(公告)日：2008-01-24

申请号：US11459060

申请日：2006-07-21

申请人： Rajat Chaudhry ,  Sang H. Dhong ,  Gilles Gervais ,  Danny J. Klema

发明人： Rajat Chaudhry ,  Sang H. Dhong ,  Gilles Gervais ,  Danny J. Klema

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F1/3203 ,  G06F2217/78 ,  Y02D10/124

摘要： A power estimation system uses a hardware accelerated simulator to advance simulation to a point of interest for power estimation. The hardware accelerated simulator generates a checkpoint file, which is then used by a software simulator to initiate simulation of the processor design model for power estimation. An on-the-fly power estimator provides power calculations in memory. Thus, the power estimation system described herein isolates instruction sequences to determine portions of software code that may consume excess power or generate noise and to provide a more accurate power estimate on the fly.

摘要翻译： 功率估计系统使用硬件加速模拟器将模拟推进到功率估计的兴趣点。 硬件加速模拟器产生一个检查点文件，然后由软件模拟器用来启动用于功率估计的处理器设计模型的仿真。 动态功率估计器在存储器中提供功率计算。 因此，本文描述的功率估计系统隔离指令序列以确定可消耗过多功率或产生噪声的软件代码的部分并且在飞行中提供更准确的功率估计。

公开(公告)号：US20080013388A1

公开(公告)日：2008-01-17

申请号：US11457507

申请日：2006-07-14

申请人： Toru Asano ,  Sang H. Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

发明人： Toru Asano ,  Sang H. Dhong ,  Takaaki Nakazato ,  Osamu Takahashi

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/848

摘要： A memory system including a memory array with redundant wordlines is disclosed. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.

摘要翻译： 公开了一种包括具有冗余字线的存储器阵列的存储器系统。 存储器系统包括存储器字线测试器，其确定任何字线是否存在缺陷。 存储器系统还包括使用其间数量减少的控制信号线有效地耦合到字线移位逻辑的解码器冗余逻辑。 移位逻辑将有缺陷的字线转移到阵列中的上游字线以绕过有缺陷的字线。

公开(公告)号：US5292678A

公开(公告)日：1994-03-08

申请号：US882735

申请日：1992-05-14

申请人： Sang H. Dhong ,  Wei Hwang

发明人： Sang H. Dhong ,  Wei Hwang

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/265

CPC分类号： H01L27/10805 ,  H01L27/10829 ,  Y10S257/907

摘要： A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in a row direction while the word lines run in a column direction. Transfer transistors are designed to be shared with the same drain junction and the same bit line contact in order to save area. A choice of at least two described embodiments are provided. In one embodiment, referred to as the offset bit line structure, the bit lines are constructed by using two layers of interconnection lines to connect the interdigitated cells associated to it. By connecting the bit line contacts and with two different interconnecting layers and in an alternating row order, the true and complement bit lines and will run parallel to both sides of the memory array. In another embodiment, referred to as the side wall bit line structure, the bit lines are constructed by using the conductive side wall spacer rails to connect the interdigitated cells associated to it. By connecting the side wall bit line contacts with two sided-side wall spacer rails in an alternating row order, the true and complement bit lines will run parallel to both sides of the memory array.

摘要翻译： 公开了一种用于未来一代高密度半导体存储器设计的新的叉指折叠位线（IFBL）架构。 在架构中，基本交叉点存储单元以行和列正交组织以形成阵列矩阵。 位线在行方向上运行，而字线在列方向上运行。 传输晶体管被设计为与相同的漏极结和相同的位线接触共享，以节省面积。 提供了至少两个描述的实施例的选择。 在一个实施例中，称为偏移位线结构，位线通过使用两层互连线来连接与其相关联的交叉指示的单元来构造。 通过连接位线触点和两个不同的互连层并以交替的行顺序，真和补码位线将平行于存储器阵列的两侧延伸。 在称为侧壁位线结构的另一实施例中，位线通过使用导电侧壁间隔轨道来连接与其相关联的叉指式电池而构成。 通过以交替的行顺序将侧壁位线触点与双面侧壁间隔轨连接，真和补补位线将平行于存储器阵列的两侧延伸。