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    COMPONENT RELIABILITY BUDGETING SYSTEM
    12.
    发明申请
    COMPONENT RELIABILITY BUDGETING SYSTEM 有权
    组件可靠性预算系统

    公开(公告)号：US20090033308A1

    公开(公告)日：2009-02-05

    申请号：US12245360

    申请日：2008-10-03

    申请人： Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Stephen H. Tang

    发明人： Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De ,  Stephen H. Tang

    IPC分类号： G05F5/00

    CPC分类号： G06F1/206 ,  Y02D10/16

    摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

    摘要翻译： 系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及 温度信息。 一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。

    Memory cell without halo implant
    15.
    发明授权
    Memory cell without halo implant 有权
    无光晕植入的记忆细胞

    公开(公告)号：US07355246B2

    公开(公告)日：2008-04-08

    申请号：US11268430

    申请日：2005-11-07

    申请人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Stephen H. Tang ,  Dinesh Somasekhar ,  Fabrice Paillet ,  Muhammad M. Khellah ,  Yibin Ye ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： H01L29/76

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/0207 ,  H01L27/0214 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108

    摘要： Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

    摘要翻译： 一些实施例提供一种存储单元，其包括掺杂有第一类型的电荷载体的体区，设置在体区中的源极区，并掺杂有第二类型的电荷载流子，以及设置在体区中的掺杂电荷 第二种载体。 根据一些实施例，身体区域，源区域和漏极区域在第一方向上定向，身体区域和源区域形成第一结，并且体区域和漏区域形成第二结。 此外，在第一结无偏置的情况下，从体区到源极区的第一结的导电率基本上小于从体区到漏区的第二结的导电率，在第二结 是不偏不倚的 一些实施例还包括在第二方向上取向的晶体管，其中第二方向不平行于第一方向。

    Gating for dual edge-triggered clocking
    19.
    发明授权
    Gating for dual edge-triggered clocking 失效
    门控双边沿触发时钟

    公开(公告)号：US07109776B2

    公开(公告)日：2006-09-19

    申请号：US10947869

    申请日：2004-09-23

    申请人： James W. Tschanz ,  Dinesh Somasekhar ,  Vivek K. De

    发明人： James W. Tschanz ,  Dinesh Somasekhar ,  Vivek K. De

    IPC分类号： H03K3/013

    CPC分类号： G06F1/10

    摘要： Some embodiments provide reception of a clock signal, reception of a gating signal, and output of a gated clock signal to a dual edge-triggered-clocked circuit. The gated clock signal is based on the clock signal and on the gating signal.

    摘要翻译： 一些实施例提供时钟信号的接收，门控信号的接收以及门控时钟信号输出到双边沿触发时钟电路。 门控时钟信号基于时钟信号和门控信号。