公开(公告)号：US20090237996A1

公开(公告)日：2009-09-24

申请号：US12052300

申请日：2008-03-20

申请人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

发明人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

IPC分类号： G11C11/34 ,  H01L29/78

CPC分类号： G11C14/0018 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分 行的存储单元。

公开(公告)号：US20090129188A1

公开(公告)日：2009-05-21

申请号：US11986333

申请日：2007-11-20

申请人： Tae Kim ,  Howard C. Kirsch

发明人： Tae Kim ,  Howard C. Kirsch

IPC分类号： G11C7/08

CPC分类号： G11C7/08 ,  G11C7/062

摘要： Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.

摘要翻译： 针对电压补偿的读出放大器描述实施例。 一个这样的感测放大器包括分别耦合到一对晶体管的一对数字线节点。 第一对开关适于将晶体管的栅极交叉耦合到相应的数字线节点，并且第二对开关适于将晶体管的栅极耦合到电压源。 第一和第二对开关耦合到晶体管的相应栅极，独立于一对晶体管分别耦合到数字线节点。

公开(公告)号：US20080176378A1

公开(公告)日：2008-07-24

申请号：US12057643

申请日：2008-03-28

申请人： Shubneesh Batra ,  Howard C. Kirsch ,  Gurtej S. Sandhu ,  Xianfeng Zhou ,  Chih-Chen Cho

发明人： Shubneesh Batra ,  Howard C. Kirsch ,  Gurtej S. Sandhu ,  Xianfeng Zhou ,  Chih-Chen Cho

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.

摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

公开(公告)号：US07365384B2

公开(公告)日：2008-04-29

申请号：US11588748

申请日：2006-10-27

申请人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

发明人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10888

摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

摘要翻译： 存储器件包括大致平行于并沿着有源区域的相关带形成的隔离沟槽。 导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。 位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

公开(公告)号：US07254074B2

公开(公告)日：2007-08-07

申请号：US11074518

申请日：2005-03-07

申请人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

发明人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

公开(公告)号：US06925019B2

公开(公告)日：2005-08-02

申请号：US10830888

申请日：2004-04-22

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： G11C7/10 ,  G11C8/02 ,  G11C7/00

CPC分类号： G11C7/1096 ,  G11C7/1048 ,  G11C7/1078

摘要： A system and method for coupling read data signals and write data signals through I/O lines of a memory array. Precharge circuits precharge alternating signal lines to high and low precharge voltages. An accelerate high circuit coupled to each of the I/O lines that has been precharged low detects an increase in the voltage of the I/O line above the precharge low voltage. The accelerate high circuit then drives the I/O line toward a high voltage, such as VCC. Similarly, an accelerate low circuit coupled to each of the I/O lines that has been precharged high detects a decrease in the voltage of the I/O line below the precharge high voltage. The accelerate low circuit then drives the I/O line to a low voltage, such as ground.

摘要翻译： 用于通过存储器阵列的I / O线耦合读取数据信号和写入数据信号的系统和方法。 预充电电路将交变信号线预充电到高和低预充电电压。 连接到已经预充电的每个I / O线的加速高电平检测到I / O线的电压在预充电低电压之上的增加。 然后，加速高电路将I / O线驱动到高电压，例如V CC CC。 类似地，耦合到已经预充电的每个I / O线的加速低电平检测到I / O线的电压降低到预充电高电压以下。 加速低电压然后将I / O线驱动到低电压，例如接地。

公开(公告)号：US06888769B2

公开(公告)日：2005-05-03

申请号：US10231626

申请日：2002-08-29

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068

摘要： The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.

摘要翻译： 通过将有效数字线偏置为轻微的正电压来降低DRAM的所需刷新率，以减少未被访问的存储器单元中的存取晶体管的次阈值电流泄漏。 轻微的正电压由电压调节器电路提供，该电压调节器电路使用在阱中制造的一个或多个双极晶体管，其将双极晶体管与衬底的其余部分电隔离。 由电压调节器提供的电压优选地通过用来自电压调节器的电压为DRAM中的每个n检测放大器供电而耦合到存取晶体管。

公开(公告)号：US06735103B2

公开(公告)日：2004-05-11

申请号：US10231680

申请日：2002-08-29

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： G11C502

CPC分类号： G11C11/4074 ,  G11C7/18 ,  G11C11/4097 ,  G11C2211/4068

摘要： Selective coupling devices directed by coupling controllers prevent cell plate and/or substrate disturbances from causing memory cell read and refresh errors in open digit line array memory devices. Using selective decoupling devices, when memory cells in an active row store an appreciably unbalanced number of either zeroes or ones, reading the cells generates a voltage transient in the cell plate and/or substrate that can be coupled to a reference digit line because the cell plates and/or substrates of the active sub-array are normally coupled to the cell plates and/or substrates of the reference arrays. By decoupling the cell plate and/or substrate of the active sub-array from the cell plates and/or substrates of the reference arrays, any coupling of the voltage transients to reference digit lines is reduced.

摘要翻译： 由耦合控制器引导的选择耦合器件防止电池板和/或衬底干扰在开放数字线阵列存储器件中引起存储单元读取和刷新错误。 使用选择性去耦装置，当活动行中的存储器单元存储零或非零数目的明显不平衡数量时，读取单元会在单元板和/或基板中产生可耦合到参考数字线的电压瞬变，因为单元 有源子阵列的板和/或基板通常耦合到参考阵列的单元板和/或基板。 通过将有源子阵列的单元板和/或衬底与参考阵列的单元板和/或衬底分离，减小了电压瞬变对参考数字线的任何耦合。

公开(公告)号：US5488579A

公开(公告)日：1996-01-30

申请号：US235735

申请日：1994-04-29

申请人： Umesh Sharma ,  Jim Hayden ,  Howard C. Kirsch

发明人： Umesh Sharma ,  Jim Hayden ,  Howard C. Kirsch

IPC分类号： H01L21/8244 ,  H01L21/8247 ,  G11C11/40

CPC分类号： H01L27/11517 ,  H01L27/11

摘要： A nonvolatile SRAM cell (20) includes a six-transistor SRAM cell portion (22) and a three-transistor nonvolatile memory portion (30). The nonvolatile memory portion (30) is connected to one storage node (101) of the SRAM cell portion (22). The nonvolatile SRAM cell (20) is three-dimensionally integrated in four layers of polysilicon. The nonvolatile memory portion (30) includes a thin film memory cell (32) having an oxide-nitride-oxide structure (41), and is programmable with a relatively low programming voltage. The three-dimensional integration of the nonvolatile SRAM cell (20) and relatively low programming voltage results in lower power consumption and smaller cell size.

摘要翻译： 非易失性SRAM单元（20）包括六晶体管SRAM单元部分（22）和三晶体管非易失性存储器部分（30）。 非易失性存储器部分（30）连接到SRAM单元部分（22）的一个存储节点（101）。 非易失性SRAM单元（20）三维地集成在四层多晶硅中。 非易失性存储器部分（30）包括具有氧化物 - 氧化物 - 氧化物结构（41）的薄膜存储单元（32），并且可编程的编程电压相对较低。 非易失性SRAM单元（20）的三维集成和相对低的编程电压导致较低的功耗和较小的单元尺寸。

公开(公告)号：US5459083A

公开(公告)日：1995-10-17

申请号：US24719

申请日：1993-03-01

申请人： Ravi Subrahmanyan ,  Howard C. Kirsch

发明人： Ravi Subrahmanyan ,  Howard C. Kirsch

IPC分类号： H01L27/07 ,  H01L21/265

CPC分类号： H01L27/0722 ,  Y10S148/009

摘要： The present invention includes a BiMOS device having an MOS transistor that triggers a bipolar transistor, wherein the base and channel region are formed within a well region that electrically floats. The present invention also includes a BiMOS device having separate regions for the collector and drain regions and for the base and channel regions. The present invention further includes processes for forming the BiMOS devices. The BiMOS device may include a floating well region. The BiMOS device may include both low voltage MOS logic transistors and a high voltage or high power bipolar transistor. A low voltage or low power bipolar transistor may also be used. Separate drain, collector, base, and channel regions allow the bipolar transistor performance to be optimized independently of the MOS transistor, which may have its performance independently optimized, too. A plurality of MOS logic transistors, such as an AND or an OR gate may be used in the BiMOS device.

摘要翻译： 本发明包括具有触发双极晶体管的MOS晶体管的BiMOS器件，其中基极和沟道区域形成在电漂浮的阱区内。 本发明还包括具有用于集电极和漏极区域以及基极和沟道区域的分离区域的BiMOS器件。 本发明还包括用于形成BiMOS器件的工艺。 BiMOS装置可以包括浮动井区域。 BiMOS器件可以包括低电压MOS逻辑晶体管和高电压或高功率双极晶体管。 也可以使用低电压或低功率双极晶体管。 单独的漏极，集电极，基极和沟道区域可以独立于可能具有独立优化的MOS晶体管来优化双极晶体管性能。 在BiMOS器件中可以使用多个MOS逻辑晶体管，诸如AND或OR门。