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公开(公告)号：US07354812B2
公开(公告)日：2008-04-08
申请号：US10931946
申请日：2004-09-01
IPC分类号： H01L21/337 , H01L21/8238 , H01L21/8249 , H01L21/336 , H01L21/331 , H01L21/76 , H01L33/00 , H01L29/76 , H01L31/00 , H01L29/00
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US20080176378A1
公开(公告)日：2008-07-24
申请号：US12057643
申请日：2008-03-28
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US07939394B2
公开(公告)日：2011-05-10
申请号：US12057643
申请日：2008-03-28
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US20060043455A1
公开(公告)日：2006-03-02
申请号：US10931946
申请日：2004-09-01
申请人： Shubneesh Batra , Howard Kirsch , Gurtej Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard Kirsch , Gurtej Sandhu , Xianfeng Zhou , Chih-Chen Cho
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US20090021986A1
公开(公告)日：2009-01-22
申请号：US12236999
申请日：2008-09-24
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/66833 , H01L29/792 , H01L29/7926 , Y10S438/954
摘要： An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive type first well region. The operating method includes applying a first voltage to a control gate, a second voltage to a drain region, and a third voltage to a source region. Besides, a channel F-N tunneling effect is employed to program a memory cell.
摘要翻译： 用于非易失性存储器件的操作方法适用于其中设置衬底的非易失性存储器件。 衬底包括沟槽，设置在衬底中的第一导电类型的第一阱区域和设置在第一导电类型的第一阱区域上方的第二导电类型的第二阱区域。 操作方法包括将第一电压施加到控制栅极，将第二电压施加到漏极区域，并将第三电压施加到源极区域。 此外，采用信道F-N隧道效应来对存储器单元进行编程。
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公开(公告)号：US20070263448A1
公开(公告)日：2007-11-15
申请号：US11778657
申请日：2007-07-17
申请人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
发明人： Wei-Zhe Wong , Ching-Sung Yang , Chih-Chen Cho
CPC分类号： G11C16/0416 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
摘要翻译： 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。
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7.发明申请公开(公告)号：US20070108504A1
公开(公告)日：2007-05-17
申请号：US11308507
申请日：2006-03-31
申请人： Yung-Chung Lee , Hann-Ping Hwang , Chin-Chung Wang , Chih-Ming Chao , Saysamone Pittikoun , Chih-Chen Cho
发明人： Yung-Chung Lee , Hann-Ping Hwang , Chin-Chung Wang , Chih-Ming Chao , Saysamone Pittikoun , Chih-Chen Cho
IPC分类号： H01L29/788 , H01L29/76 , H01L21/336
CPC分类号： H01L29/792 , G11C16/0483 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： A non-volatile memory having a plurality of gate structures, a plurality of charge storage layers and two doped regions is provided. The gate structures are disposed on the substrate and connected in series. The charge storage layers are disposed between every two neighboring gate structures respectively. The gate structures and the charge storage layers form a memory cell column. The two doped regions are disposed in the substrate at both sides of the memory cell column.
摘要翻译： 提供具有多个栅极结构，多个电荷存储层和两个掺杂区域的非易失性存储器。 栅极结构设置在基板上并串联连接。 电荷存储层分别设置在每两个相邻栅极结构之间。 栅极结构和电荷存储层形成存储单元列。 两个掺杂区域在存储单元列的两侧设置在基板中。
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8.发明申请公开(公告)号：US20060039200A1
公开(公告)日：2006-02-23
申请号：US10907031
申请日：2005-03-17
申请人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
发明人： Ching-Sung Yang , Wei-Zhe Wong , Chih-Chen Cho
IPC分类号： G11C7/10
CPC分类号： G11C16/0483 , G11C16/0466 , H01L27/115 , H01L27/11519 , H01L27/11568
摘要： A non-volatile memory including a plurality of memory units is provided. Each of the memory units includes a first memory cell and a second memory cell. The first memory cell is disposed over the substrate. The second memory cell is disposed next to the sidewall of the first memory cell and over the substrate. The first memory cell includes a first gate disposed over the substrate, a first composite dielectric layer disposed between the first gate and the substrate. The second memory cell includes a second gate disposed over the substrate and a second composite dielectric layer disposed between the second gate and the substrate and between the second gate and the first memory cell. Each of the first and second composite dielectric layers includes a bottom dielectric layer, a charge-trapping layer and a top dielectric layer.
摘要翻译： 提供包括多个存储单元的非易失性存储器。 每个存储单元包括第一存储单元和第二存储单元。 第一存储单元设置在衬底上。 第二存储单元设置在第一存储单元的侧壁旁边且在衬底上。 第一存储单元包括设置在衬底上的第一栅极，设置在第一栅极和衬底之间的第一复合介电层。 第二存储单元包括设置在衬底上的第二栅极和设置在第二栅极和衬底之间以及第二栅极和第一存储单元之间的第二复合电介质层。 第一和第二复合电介质层中的每一个包括底部电介质层，电荷俘获层和顶部电介质层。
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公开(公告)号：US20050151198A1
公开(公告)日：2005-07-14
申请号：US11057302
申请日：2005-02-11
申请人： Zhongze Wang , Chih-Chen Cho
发明人： Zhongze Wang , Chih-Chen Cho
IPC分类号： G11C11/412 , H01L21/768 , H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： G11C11/4125 , G11C11/412 , H01L21/76885 , H01L27/11 , H01L27/1104
摘要： A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.
摘要翻译： 具有金属填充的静态随机存取存储器单元以形成用于增加存储单元的电容的电容器。 更具体地说，一种半导体器件，包括具有形成在该结构的上表面上的上表面和接触表面的结构。 介电材料在接触表面上与第一导电节点和延伸超出电介质材料的第二导电节点形成。 电介质隔板围绕第一和第二导电节点形成，并且导电元件形成在电介质间隔件之间。 导电元件和间隔件形成电容器而不实施附加的掩蔽步骤。
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公开(公告)号：US06858937B2
公开(公告)日：2005-02-22
申请号：US09517314
申请日：2000-03-02
申请人： Chih-Chen Cho
发明人： Chih-Chen Cho
IPC分类号： H01L21/768 , H01L23/48 , H01L23/58
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited withinan etched via and is contacted with the conductive plug.
摘要翻译： 对半导体器件及其制造方法进行说明。 在形成半导体器件期间，由耐蚀刻材料形成硬掩模。 掩模防止蚀刻剂蚀刻导电塞附近的电介质材料内的区域。 掩模可以由氮化物形成。 然后将导电材料沉积在蚀刻通孔内并与导电塞接触。
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