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公开(公告)号：US07354812B2
公开(公告)日：2008-04-08
申请号：US10931946
申请日：2004-09-01
IPC分类号： H01L21/337 , H01L21/8238 , H01L21/8249 , H01L21/336 , H01L21/331 , H01L21/76 , H01L33/00 , H01L29/76 , H01L31/00 , H01L29/00
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US07939394B2
公开(公告)日：2011-05-10
申请号：US12057643
申请日：2008-03-28
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US20080176378A1
公开(公告)日：2008-07-24
申请号：US12057643
申请日：2008-03-28
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US20060043455A1
公开(公告)日：2006-03-02
申请号：US10931946
申请日：2004-09-01
申请人： Shubneesh Batra , Howard Kirsch , Gurtej Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard Kirsch , Gurtej Sandhu , Xianfeng Zhou , Chih-Chen Cho
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译： 集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。 电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。 然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。 然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。 这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。
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公开(公告)号：US20090302322A1
公开(公告)日：2009-12-10
申请号：US12492991
申请日：2009-06-26
IPC分类号： H01L29/786 , H01L21/20
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
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公开(公告)号：US07566907B2
公开(公告)日：2009-07-28
申请号：US12135761
申请日：2008-06-09
IPC分类号： H01L21/00
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。
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公开(公告)号：US06890842B2
公开(公告)日：2005-05-10
申请号：US09902277
申请日：2001-07-09
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/04 , H01L29/786 , H01L21/311
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与 多晶薄膜层。
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公开(公告)号：US06333256B2
公开(公告)日：2001-12-25
申请号：US09219236
申请日：1998-12-22
申请人： Gurtej S. Sandhu , Shubneesh Batra
发明人： Gurtej S. Sandhu , Shubneesh Batra
IPC分类号： H01L21311
CPC分类号： H01L21/76802 , Y10S438/948 , Y10S438/95
摘要： The invention includes a semiconductor processing method which comprises forming a first material layer over a substrate. A second material layer is formed over the first material layer. Photoresist is deposited over the second material layer, and an opening is formed within the photoresist to the second material layer. The second material layer is etched through the photoresist opening to a degree insufficient to outwardly expose the first material layer. The photoresist is then stripped from the substrate. Subsequently, the second material layer and the first material layer are blanket etched.
摘要翻译： 本发明包括半导体处理方法，其包括在衬底上形成第一材料层。 在第一材料层上形成第二材料层。 光致抗蚀剂沉积在第二材料层上，并且在光致抗蚀剂内形成到第二材料层的开口。 通过光致抗蚀剂开口蚀刻第二材料层至不足以向外暴露第一材料层的程度。 然后将光致抗蚀剂从基底剥离。 随后，对第二材料层和第一材料层进行全面蚀刻。
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9.发明授权
公开(公告)号：US6114735A
公开(公告)日：2000-09-05
申请号：US347432
申请日：1999-07-02
申请人： Shubneesh Batra , Gurtej S. Sandhu
发明人： Shubneesh Batra , Gurtej S. Sandhu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/786 , H01L29/76
CPC分类号： H01L21/28194 , H01L21/28008 , H01L21/28088 , H01L21/28202 , H01L29/42368 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66765 , H01L29/78678
摘要： The invention includes field effect transistors and methods of forming field effect transistors. In one implementation, a field effect transistor includes a semiconductive channel region and a gate construction operatively proximate the channel region. The gate construction includes a conductive gate region and a gate dielectric region intermediate the channel region and the conductive gate region. The gate dielectric region includes a Ta.sub.2 O.sub.5 comprising layer and a SiO.sub.2 comprising layer intermediate the Ta.sub.2 O.sub.5 comprising layer and the channel region. The conductive gate region includes at least two different material layers, with one of the at least two layers comprising a first conductive material and another of the at least two layers comprising a conductive metal nitride which is received intermediate the Ta.sub.2 O.sub.5 comprising layer and the one layer. In one implementation in a field effect transistor gate, the gate dielectric region includes a Ta.sub.2 O.sub.5 comprising layer and a SiO.sub.2 comprising layer intermediate the Ta.sub.2 O.sub.5 comprising layer and the conductive gate region. The gate dielectric layer region is substantially void of a SiO.sub.2 comprising layer intermediate the Ta.sub.2 O.sub.5 comprising layer and the conductive gate region.
摘要翻译： 本发明包括场效应晶体管和形成场效应晶体管的方法。 在一个实现中，场效应晶体管包括可操作地接近沟道区的半导体沟道区和栅结构。 栅极结构包括在沟道区域和导电栅极区域之间的导电栅极区域和栅极电介质区域。 栅极电介质区域包括包含Ta 2 O 5的层和包含Ta 2 O 5的层和沟道区域之间的包含SiO 2的层。 所述导电栅极区包括至少两个不同的材料层，所述至少两个层中的一个包括第一导电材料，并且所述至少两个层中的另一层包括导电金属氮化物，所述导电金属氮化物被接收在包含Ta 2 O 5的层之中，并且所述一层 。 在场效应晶体管栅极的一个实现中，栅极电介质区域包括包含Ta 2 O 5的层和包含Ta 2 O 5的层和导电栅极区域之间的包含SiO2的层。 栅极电介质层区域基本上不含包含Ta 2 O 5的层和导电栅极区域的包含SiO 2的层。
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公开(公告)号：US07825414B2
公开(公告)日：2010-11-02
申请号：US12257614
申请日：2008-10-24
IPC分类号： H01L21/00
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译： 相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。 薄膜晶体管可以被制造为底部门控或顶部门控。 可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。 优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界，但是足够低以防止含氟层与 多晶薄膜层。
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