公开(公告)号：US20130075723A1

公开(公告)日：2013-03-28

申请号：US13671638

申请日：2012-11-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Ryosuke Watanabe ,  Junichiro Sakata ,  Kengo Akimoto ,  Akiharu Miyanaga ,  Takuya Hirohashi ,  Hideyuki Kishida

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/45 ,  H01L29/78606 ,  H01L29/78696

Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.

Abstract translation: 在使用氧化物半导体形成沟道形成区域的沟道保护薄膜晶体管中，使用通过热处理脱水或脱氢的氧化物半导体层作为有源层，包括纳米晶体的晶体区域包含在表面 并且其余部分是无定形的或由非晶/非晶体和微晶体的混合物形成，其中非晶区域用微晶点缀。 通过使用具有这种结构的氧化物半导体层，可以防止由于进入水分或从表面部分去除氧气或从表面部分排出而引起的n型变化和产生寄生通道，并且与源极接触电阻 可以减少漏电极。

公开(公告)号：US10115831B2

公开(公告)日：2018-10-30

申请号：US15220532

申请日：2016-07-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Ryosuke Watanabe ,  Junichiro Sakata ,  Kengo Akimoto ,  Akiharu Miyanaga ,  Takuya Hirohashi ,  Hideyuki Kishida

IPC: H01L29/04 ,  H01L29/786 ,  H01L27/12 ,  H01L29/45

Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.

公开(公告)号：US09853167B2

公开(公告)日：2017-12-26

申请号：US15090937

申请日：2016-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Ryosuke Watanabe ,  Junichiro Sakata ,  Kengo Akimoto ,  Akiharu Miyanaga ,  Takuya Hirohashi ,  Hideyuki Kishida

IPC: H01L29/12 ,  H01L29/786 ,  H01L27/12 ,  H01L29/04 ,  H01L21/263 ,  H01L29/66 ,  H01L29/24 ,  H01L29/417

CPC classification number: H01L29/78696 ,  H01L21/2636 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/12 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869

Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

公开(公告)号：US09595435B2

公开(公告)日：2017-03-14

申请号：US14055970

申请日：2013-10-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi Tsubuku ,  Ryosuke Watanabe ,  Noritaka Ishihara ,  Masashi Oota

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/02422 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02664 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78693

Abstract: To form an oxide semiconductor film with a low density of localized levels. To improve electric characteristics of a semiconductor device including the oxide semiconductor. After oxygen is added to an oxide film containing In or Ga in contact with an oxide semiconductor film functioning as a channel, heat treatment is performed to make oxygen in the oxide film containing In or Ga transfer to the oxide semiconductor film functioning as a channel, so that the amount of oxygen vacancies in the oxide semiconductor film is reduced. Further, an oxide film containing In or Ga is formed, oxygen is added to the oxide film, an oxide semiconductor film is formed over the oxide film, and then heat treatment is performed.

Abstract translation: 形成具有低密度局部化水平的氧化物半导体膜。 为了改善包括氧化物半导体的半导体器件的电特性。 在与用作沟道的氧化物半导体膜接触的含有In或Ga的氧化物膜上加氧后，进行热处理，使含有In或Ga的氧化物膜中的氧转移到作为通道发挥作用的氧化物半导体膜， 使得氧化物半导体膜中的氧空位量减少。 此外，形成含有In或Ga的氧化物膜，在氧化膜上添加氧，在氧化膜上形成氧化物半导体膜，然后进行热处理。

公开(公告)号：US09536755B2

公开(公告)日：2017-01-03

申请号：US14217519

申请日：2014-03-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryosuke Watanabe ,  Hidekazu Takahashi ,  Takuya Tsurume

IPC: H01L21/56 ,  H01L21/67 ,  B32B37/20 ,  G06K19/077 ,  H01L21/683 ,  H01L27/12

CPC classification number: H01L21/56 ,  B32B37/20 ,  B32B2305/342 ,  B42D25/45 ,  B42D2033/46 ,  G06K19/07718 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/67126 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6835 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68318 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2924/0002 ,  Y10T156/1089 ,  Y10T156/1093 ,  Y10T156/1712 ,  H01L2924/00

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract translation: 本发明的目的是提高密封薄膜集成电路的生产效率并防止损坏和断裂。 此外，本发明的另一个目的是防止薄膜集成电路在运输中受损，并且使得更容易处理薄膜集成电路。 本发明提供了一种层压系统，其中辊子用于供应用于密封的基板，接收IC芯片，分离和密封。 通过旋转辊可以连续地进行多个薄膜集成电路的分离，密封和接收; 从而可以极大地提高生产效率。 此外，由于使用了彼此相对的一对辊，所以能够容易地密封薄膜集成电路。

公开(公告)号：US08890159B2

公开(公告)日：2014-11-18

申请号：US13953428

申请日：2013-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masashi Tsubuku ,  Ryosuke Watanabe ,  Masashi Oota ,  Noritaka Ishihara ,  Koki Inoue

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/786 ,  H01L29/24

CPC classification number: H01L29/1054 ,  H01L22/14 ,  H01L29/247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

Abstract translation: 提供了不容易引起晶体管的电特性变化并且具有高稳定性的氧化物半导体层叠膜。 此外，提供了在其沟道形成区域中包括氧化物半导体层叠膜并且具有稳定的电特性的晶体管。 氧化物半导体层叠膜包括依次堆叠并且各自含有铟，镓和锌的第一氧化物半导体层，第二氧化物半导体层和第三氧化物半导体层。 第二氧化物半导体层中的铟的含量百分比高于第一氧化物半导体层和第三氧化物半导体层中的铟的含量百分比，并且通过CPM测量的氧化物半导体层叠膜的吸收系数低于或等于 在1.5eV至2.3eV的能量范围内等于3×10-3 / cm。