公开(公告)号：US20210408298A1

公开(公告)日：2021-12-30

申请号：US17295693

申请日：2019-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Erika TAKAHASHI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC: H01L29/786

Abstract: A semiconductor device with high reliability is provided. A first conductor and a second conductor are provided over and in contact with a first oxide. A first insulator is provided to cover the first oxide, a first conductor, and a second conductor. The first insulator includes an opening portion. The first oxide is exposed on a bottom surface of the opening portion. A side surface of the first conductor and a side surface of the second conductor are exposed on a side surface of the opening portion. A second oxide is provided in contact with the first oxide, the side surface of the first conductor, and the second conductor in the opening portion. A second insulator is provided in the opening portion with the second oxide therebetween. A third conductor is provided in the opening portion with the second insulator therebetween. Lower end portions of the side surface of the first conductor and the second conductor touch an ellipse or a circle with a center above the first oxide.

公开(公告)号：US20170186858A1

公开(公告)日：2017-06-29

申请号：US15461575

申请日：2017-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Masashi TSUBUKU

IPC: H01L29/66 ,  H01L27/146 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/14616 ,  H01L27/14689 ,  H01L29/7869 ,  H01L29/78696

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US20170125450A1

公开(公告)日：2017-05-04

申请号：US15332006

申请日：2016-10-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Motomu KURATA ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02 ,  H01L21/467 ,  H01L21/463 ,  H01L21/768 ,  H01L29/786 ,  H01L23/535

CPC classification number: H01L27/1225 ,  H01L21/02565 ,  H01L21/463 ,  H01L21/467 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/78603 ,  H01L29/7869

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

公开(公告)号：US20160336457A1

公开(公告)日：2016-11-17

申请号：US15221656

申请日：2016-07-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Motomu KURATA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L29/24 ,  H01L29/247 ,  H01L29/263 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/78693 ,  H01L29/78696

Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.

公开(公告)号：US20160293766A1

公开(公告)日：2016-10-06

申请号：US15175183

申请日：2016-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Shinya SASAGAWA ,  Taiga MURAOKA ,  Hiroaki HONDA ,  Takashi HAMADA

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L21/02334 ,  H01L27/1225 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78696

Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.

Abstract translation: 准备具有绝缘表面的基板; 在基板上形成包括第一氧化物半导体层和第二氧化物半导体层的层叠膜; 在层叠膜的一部分上形成掩模层，然后进行干法蚀刻处理，从而除去保留有掩模层的区域，在其余的侧面形成反应产物 叠片 去除掩模层后，通过湿蚀刻处理去除反应产物; 源极电极和漏电极形成在堆叠膜上; 并且第三氧化物半导体层，栅极绝缘膜和栅极电极按顺序层叠并形成在堆叠膜上，以及源电极和漏电极。

公开(公告)号：US20160240684A1

公开(公告)日：2016-08-18

申请号：US15019004

申请日：2016-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yoshinobu ASAMI ,  Yutaka OKAZAKI ,  Motomu KURATA ,  Katsuaki TOCHIBAYASHI ,  Shinya SASAGAWA ,  Kensuke YOSHIZUMI ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/477 ,  H01L21/465 ,  H01L21/47 ,  H01L29/66 ,  H01L21/4757

CPC classification number: H01L29/7869 ,  H01L21/47 ,  H01L21/4757 ,  H01L21/477 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78648 ,  H01L33/00

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

Abstract translation: 提供一种小型化晶体管，具有低寄生电容的晶体管，具有高频特性的晶体管，或包括晶体管的半导体器件。 半导体器件包括第一绝缘体，第一绝缘体上的氧化物半导体，与氧化物半导体接触的第一导体和第二导体，位于第一和第二导体之上并具有到达氧化物的开口的第二绝缘体 半导体，氧化物半导体上的第三绝缘体和第二绝缘体，以及位于第三绝缘体上的第四导体。 第一导体包括第一区域和第二区域。 第二导体包括第三区域和第四区域。 第二区域面对具有第一导体的第三区域，并且第一区域之间插入第一绝缘体。 第二区域比第一区域薄。 第三区域比第四区域薄。

公开(公告)号：US20160005872A1

公开(公告)日：2016-01-07

申请号：US14755670

申请日：2015-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu KURATA ,  Ryota HODO ,  Shinya SASAGAWA ,  Yuki HATA

IPC: H01L29/786 ,  H01L23/535 ,  H01L27/092 ,  H01L29/24 ,  H01L27/12

CPC classification number: H01L27/1207 ,  H01L21/8258 ,  H01L23/485 ,  H01L23/535 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1156 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. The semiconductor device includes an oxide semiconductor layer, an electrode layer, and a contact plug. The electrode layer includes one end portion in contact with the oxide semiconductor layer and the other end portion facing the one end portion. The other end portion includes a semicircle notch portion when seen from the above. The contact plug is in contact with the semicircle notch portion.

Abstract translation: 提供一种半导体器件，占用小面积并高度集成。 半导体器件包括氧化物半导体层，电极层和接触插塞。 电极层包括与氧化物半导体层接触的一个端部和面向一个端部的另一个端部。 当从上方观察时，另一端部包括半圆形切口部分。 接触塞与半圆形切口部接触。

公开(公告)号：US20150333160A1

公开(公告)日：2015-11-19

申请号：US14813413

申请日：2015-07-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/4763 ,  H01L21/441 ,  H01L21/4757 ,  H01L29/786

CPC classification number: H01L21/02565 ,  C23C14/086 ,  C23C14/3414 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02592 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L21/441 ,  H01L21/47576 ,  H01L21/47635 ,  H01L29/045 ,  H01L29/26 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78 ,  H01L29/7869

Abstract: In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.

Abstract translation: 在氧化物半导体层中包括沟道形成区域的半导体器件中，使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触并与氧化物半导体层接触的栅极绝缘膜供给氧 通过离子注入法引入的栅极绝缘膜到氧化物半导体层。

公开(公告)号：US20150255584A1

公开(公告)日：2015-09-10

申请号：US14718763

申请日：2015-05-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Hiroshi FUJIKI

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

Abstract translation: 为了建立包括In-Sn-Zn-O类半导体的半导体器件的制造中的加工技术。 通过使用含氯气体如Cl 2，BCl 3，SiCl 4等的干蚀刻来选择性地蚀刻In-Sn-Zn-O系半导体层。 在形成源极电极层和漏电极层时，可以选择性地蚀刻与In-Sn-Zn-O系半导体层接触的导电层，同时很少去除In-Sn-Zn-O系半导体层， 除了含有氯的气体之外，还使用含有氧或氟的气体。

公开(公告)号：US20150179776A1

公开(公告)日：2015-06-25

申请号：US14629575

申请日：2015-02-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo ISOBE ,  Toshinari SASAKI ,  Shinya SASAGAWA ,  Akihiro ISHIZUKA

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02667 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

Abstract: An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.

Abstract translation: 绝缘层设置有突出的结构体，并且设置与突出结构体接触的氧化物半导体层的沟道形成区域，由此沟道形成区域沿三维方向（垂直于衬底的方向）延伸 ）。 因此，可以使晶体管小型化并且延长晶体管的有效沟道长度。 此外，突出结构体的顶表面和侧表面彼此相交的突出结构体的上端角部弯曲，并且氧化物半导体层形成为包括具有c轴的晶体 垂直于曲面。