公开(公告)号：US20060094188A1

公开(公告)日：2006-05-04

申请号：US11261820

申请日：2005-10-28

申请人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

摘要翻译： 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US20100072545A1

公开(公告)日：2010-03-25

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹陷。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

公开(公告)号：US20090233416A1

公开(公告)日：2009-09-17

申请号：US12471521

申请日：2009-05-26

申请人： Dong-Chan Kim

发明人： Dong-Chan Kim

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42336

摘要： Flash memory devices include pillar patterns formed between selected pairs of floating gates and control gate extensions that penetrate between selected pairs of floating gates are provided. Methods of fabricating the flash memory devices are also provided.

摘要翻译： 闪存器件包括形成在所选择的浮置栅极对之间的柱状图案，并且提供穿透选择的浮置栅极对之间的控制栅极延伸部分。 还提供了制造闪速存储器件的方法。

公开(公告)号：US09484219B2

公开(公告)日：2016-11-01

申请号：US14826845

申请日：2015-08-14

申请人： Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

发明人： Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

IPC分类号： H01L21/8242 ,  H01L21/311 ,  H01L27/108

CPC分类号： H01L21/31144 ,  H01L21/31111 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855

摘要： A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

摘要翻译： 制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。 该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率 相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与 第一杂质浓度。

公开(公告)号：US09190495B2

公开(公告)日：2015-11-17

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹部。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

公开(公告)号：US08252681B2

公开(公告)日：2012-08-28

申请号：US12536865

申请日：2009-08-06

申请人： Jeong-Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Dong-Chan Kim ,  Jong-Ryeol Yoo ,  Seong-Hoon Jeong ,  Jong-Hoon Kang

IPC分类号： H01L21/44

CPC分类号： H01L21/28061 ,  H01L21/28247 ,  H01L21/3211 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104

摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

摘要翻译： 形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。 使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。 可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。 然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。 在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

公开(公告)号：US20060231822A1

公开(公告)日：2006-10-19

申请号：US11358897

申请日：2006-02-21

申请人： Dong-Chan Kim

发明人： Dong-Chan Kim

IPC分类号： H01L47/00

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory device includes a common source region that is disposed in an active region at a side of a ground-selection gate line, being apart from the ground-selection gate line. A pair of source spacers crosses over both top edges of the common source region. A source line fills up a space between the pair of source spacers. The top surface of the source line is equal to or lower than the that of the ground-selection gate line.

公开(公告)号：US20140106567A1

公开(公告)日：2014-04-17

申请号：US14133296

申请日：2013-12-18

申请人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-Chan Kim ,  Myeong-Cheol Kim

发明人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-Chan Kim ,  Myeong-Cheol Kim

IPC分类号： H01L27/115

CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

公开(公告)号：US08691649B2

公开(公告)日：2014-04-08

申请号：US13151494

申请日：2011-06-02

申请人： Tai-Su Park ,  Jung-Sup Oh ,  Gun-Joong Lee ,  Jung-Soo An ,  Dong-Kyu Lee ,  Jung-Geun Park ,  Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Tai-Su Park ,  Jung-Sup Oh ,  Gun-Joong Lee ,  Jung-Soo An ,  Dong-Kyu Lee ,  Jung-Geun Park ,  Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

摘要翻译： 在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。 可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。 可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。 可以在栅极氧化物层上形成栅电极以填充凹部。 源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。 因此，氧化物层可以具有均匀的厚度分布和致密结构。

公开(公告)号：US07476928B2

公开(公告)日：2009-01-13

申请号：US11358897

申请日：2006-02-21

申请人： Dong-Chan Kim

发明人： Dong-Chan Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory device includes a common source region that is disposed in an active region at a side of a ground-selection gate line, being apart from the ground-selection gate line. A pair of source spacers crosses over both top edges of the common source region. A source line fills up a space between the pair of source spacers. The top surface of the source line is equal to or lower than the that of the ground-selection gate line.

摘要翻译： 闪速存储器件包括公共源极区域，其设置在与接地选择栅极线分离的接地选择栅极线侧的有源区域中。 一对源隔离物跨越共同源极区域的两个顶部边缘。 源极线填充一对源间隔物之间​​的空间。 源极线的顶面等于或低于接地选择栅极线的顶面。