公开(公告)号：US06821853B1

公开(公告)日：2004-11-23

申请号：US10159413

申请日：2002-05-31

申请人： James F. Buller ,  Scott Luning

发明人： James F. Buller ,  Scott Luning

IPC分类号： H01L218234

CPC分类号： H01L21/823468 ,  H01L21/823462

摘要： Methods of manufacturing are provided. In one aspect, a method of manufacturing is provided that includes forming first and second gate stacks on a substrate and forming an insulating layer on the substrate. The insulating layer has portions adjacent to the first stack and portions adjacent to the second gate stack. A first pair of insulating structures is formed adjacent to the first gate stack and a second pair of insulating structures is formed adjacent to the second gate stack. The first pair of insulating structures is removed. The portions of the insulating layer adjacent to the first gate stack are thickened while the second pair of insulating structures prevents thickening of the portions of the insulating film adjacent to the second gate stack. Differential insulating layer thickness for different gate devices is permitted to enable reduction in leakage currents for selected devices without harming speed performance for others.

摘要翻译： 提供制造方法。 一方面，提供一种制造方法，其包括在衬底上形成第一和第二栅极叠层并在衬底上形成绝缘层。 绝缘层具有与第一堆叠相邻的部分和与第二栅极堆叠相邻的部分。 第一对绝缘结构形成为与第一栅极堆叠相邻，并且第二对绝缘结构形成为与第二栅极堆叠相邻。 第一对绝缘结构被去除。 与第一栅极堆叠相邻的绝缘层的部分被加厚，而第二对绝缘结构防止绝缘膜的与第二栅极叠层相邻的部分的增厚。 允许不同栅极器件的差分绝缘层厚度能够减少所选器件的漏电流，而不会损害其他器件的速度性能。

公开(公告)号：US06319804B1

公开(公告)日：2001-11-20

申请号：US08624910

申请日：1996-03-27

申请人： David Greenlaw ,  Scott Luning

发明人： David Greenlaw ,  Scott Luning

IPC分类号： H01L2102

CPC分类号： H01L29/66575 ,  H01L21/28061 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention is directed toward a method for independently doping the gate and the source-drain regions of a semiconductor device. The method is initiated by the provision. of a substrate having isolation regions and a thin insulating layer. Over the substrate is formed a polysilicon layer which is doped with a first type of dopant at a first doping level. Over the polysilicon layer is formed a conducting layer of material that can withstand temperatures of 1000° C., and over the conducting layer is formed a blocking layer. The polysilicon layer, the conducting layer and the blocking layer are etched to form a gate stack. Source-drain regions are subsequently doped with a second type of dopant at a second doping level. Source-drain regions are activated in a 1000° C. heat cycle, and, subsequently, TiSi2 is formed on the source-drain regions. Contacts are then formed. The blocking layer on the gate stack need not be removed, which aids in minimizing substrate damage and in prevention of shorting a source-drain contact region to the substrate.

摘要翻译： 本发明涉及用于独立地掺杂半导体器件的栅极和源极 - 漏极区域的方法。 该方法由该条款开始。 具有隔离区域和薄绝缘层的衬底。 在衬底上形成多晶硅层，其以第一掺杂级别掺杂有第一类型的掺杂剂。 在多晶硅层上形成能够承受1000℃的温度的导电层，并且在导电层上形成阻挡层。 蚀刻多晶硅层，导电层和阻挡层以形成栅叠层。 源极 - 漏极区域随后以第二掺杂水平掺杂第二类型的掺杂剂。 源极 - 漏极区域在1000℃的热循环中被激活，随后在源极 - 漏极区域上形成TiSi 2。 然后形成接触。 栅堆叠上的阻挡层不需要去除，这有助于最小化衬底损伤并防止将源 - 漏接触区域短路到衬底。

公开(公告)号：US6107149A

公开(公告)日：2000-08-22

申请号：US325628

申请日：1999-06-04

申请人： David Wu ,  Scott Luning

发明人： David Wu ,  Scott Luning

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

摘要： A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

摘要翻译： 形成具有N沟道晶体管的CMOS半导体器件，其包括具有减小的结电容的梯度结。 通过在源极/漏极注入之后在栅电极上形成第二侧壁间隔物并且将具有高扩散率的N型杂质（例如P）离子注入到A5植入物中，然后进行活化退火来实现渐变结。

公开(公告)号：US5935867A

公开(公告)日：1999-08-10

申请号：US481895

申请日：1995-06-07

申请人： Roger Alvis ,  Scott Luning ,  Peter Griffin

发明人： Roger Alvis ,  Scott Luning ,  Peter Griffin

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L29/7835

摘要： A process for forming a shallow, lightly doped region in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a surface; growing an oxide layer on the substrate, the oxide having a thickness; depositing a layer of polysilicon on the oxide; patterning the polysilicon layer and the oxide layer to provide a gate structure; and implanting into the substrate a source and a drain region about the gate structure at an angle less than 90 degrees with respect to the surface of the substrate.

摘要翻译： 一种用于在半导体器件中形成浅的，轻掺杂区域的工艺。 该方法包括提供具有表面的半导体衬底的步骤; 在衬底上生长氧化物层，氧化物具有厚度; 在氧化物上沉积多晶硅层; 图案化多晶硅层和氧化物层以提供栅极结构; 以及相对于所述衬底的表面以小于90度的角度将围绕所述栅极结构的源极和漏极区域注入到所述衬底中。

公开(公告)号：US08030144B2

公开(公告)日：2011-10-04

申请号：US12576987

申请日：2009-10-09

申请人： Scott Luning ,  Frank Scott Johnson

发明人： Scott Luning ,  Frank Scott Johnson

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US20100308409A1

公开(公告)日：2010-12-09

申请号：US12480263

申请日：2009-06-08

申请人： Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

发明人： Frank S. Johnson ,  Scott Luning ,  Michael J. Hargrove

IPC分类号： H01L27/088 ,  H01L21/308 ,  H01L21/31 ,  H01L21/8234

CPC分类号： H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7843

摘要： FinFET structures with fins having stress-inducing caps and methods for fabricating such FinFET structures are provided. In an exemplary embodiment, a method for forming stressed structures comprises forming a first stress-inducing material overlying a semiconductor material and forming spacers overlying the first stress-inducing material. The first stress-inducing material is etched using the spacers as an etch mask to form a plurality of first stress-inducing caps. The semiconductor material is etched using the plurality of first stress-inducing caps as an etch mask.

摘要翻译： 提供具有应力诱导帽的翅片的FinFET结构和用于制造这种FinFET结构的方法。 在示例性实施例中，用于形成应力结构的方法包括形成覆盖半导体材料的第一应力诱导材料并形成覆盖第一应力诱导材料的间隔物。 使用间隔物作为蚀刻掩模蚀刻第一应力诱导材料，以形成多个第一应力诱导帽。 使用多个第一应力诱导盖作为蚀刻掩模蚀刻半导体材料。

公开(公告)号：US20060272574A1

公开(公告)日：2006-12-07

申请号：US11147600

申请日：2005-06-07

申请人： Andrew Waite ,  Scott Luning

发明人： Andrew Waite ,  Scott Luning

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/823807

摘要： Methods for manufacturing an integrated circuit are provided. An exemplary method comprises the step of providing a silicon substrate having a first crystalline orientation. A silicon layer having a second crystalline orientation is bonded to the silicon substrate. The second crystalline orientation is different from the first crystalline orientation. The silicon layer is etched to expose a portion of the silicon substrate and an amorphous silicon layer is deposited on the exposed portion. The amorphous silicon layer is transformed into a regrown crystalline silicon layer having the first crystalline orientation. A first field effect transistor is formed on the silicon layer and a second field effect transistor is formed on the regrown crystalline silicon layer.

摘要翻译： 提供了制造集成电路的方法。 一种示例性方法包括提供具有第一晶体取向的硅衬底的步骤。 具有第二结晶取向的硅层与硅衬底接合。 第二结晶取向与第一结晶取向不同。 蚀刻硅层以暴露硅衬底的一部分，并且非晶硅层沉积在暴露部分上。 将非晶硅层转变成具有第一晶体取向的再结晶的晶体硅层。 在硅层上形成第一场效应晶体管，在再生晶体硅层上形成第二场效应晶体管。

公开(公告)号：US07138320B2

公开(公告)日：2006-11-21

申请号：US10974232

申请日：2004-10-24

申请人： Ralf van Bentum ,  Scott Luning ,  Andy Wei

发明人： Ralf van Bentum ,  Scott Luning ,  Andy Wei

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78687

摘要： By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In particular, the stress-inducing material formed adjacent to the gate electrode structure exerts compressive or tensile stress, depending on the type of material deposited, thereby also enhancing the mobility of the charge carriers in a channel region of the transistor element.

摘要翻译： 通过优选通过半导体层的局部氧化来凹入半导体层，可以通过随后的外延生长工艺在栅极电极结构附近的薄化半导体层中引入应力诱导材料和/或掺杂物种类。 特别地，与栅电极结构相邻形成的应力诱导材料根据所沉积材料的类型施加压缩或拉伸应力，从而也增强了晶体管元件的沟道区中电荷载流子的迁移率。

公开(公告)号：US06972478B1

公开(公告)日：2005-12-06

申请号：US11075774

申请日：2005-03-07

申请人： Andrew M. Waite ,  Scott Luning

发明人： Andrew M. Waite ,  Scott Luning

IPC分类号： H01L21/20 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L21/2007 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7833

摘要： An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of crystalline orientation and a second region of crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substrate. At least one field effect transistor is formed in the layer of silicon on insulator, at least one P-channel field effect transistor is formed in the second region of crystalline orientation, and at least one N-channel field effect transistor is formed in the first region of crystalline orientation.

摘要翻译： 提供集成电路及其制造方法。 集成电路包括具有<100>晶体取向的第一区域和<110>晶体取向的第二区域的体硅衬底。 绝缘体上的一层覆盖在体硅衬底的一部分上。 在绝缘体上的硅层中形成至少一个场效应晶体管，在<110>晶取向的第二区域中形成至少一个P沟道场效应晶体管，并形成至少一个N沟道场效应晶体管 在<100>晶体取向的第一区域。

公开(公告)号：US06806126B1

公开(公告)日：2004-10-19

申请号：US10236200

申请日：2002-09-06

申请人： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

发明人： Scott Luning ,  Karsten Wieczorek ,  Thorsten Kammler

IPC分类号： H01L21338

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  Y10S257/90

摘要： An insulated gate semiconductor device (100) having reduced gate resistance and a method for manufacturing the semiconductor device (100). A gate structure (112) is formed on a major surface (104) of a semiconductor substrate (102). Successive nitride spacers (118, 128) are formed adjacent the sidewalls of the gate structure (112). The nitride spacers (118, 128) are etched and recessed using a single etch to expose the upper portions (115A, 117A) of the gate structure (112). Source (132) and drain (134) regions are formed in the semiconductor substrate (102). Silicide regions (140, 142, 144) are formed on the top surface (109) and the exposed upper portions (115A, 117A) of the gate structure (112) and the source region (132) and the drain region (134). Electrodes (150, 152, 154) are formed in contact with the silicide (140, 142, 144) of the respective gate structure (112), source region (132), and the drain region (134).

摘要翻译： 一种具有降低的栅极电阻的绝缘栅极半导体器件（100）和用于制造半导体器件（100）的方法。 栅极结构（112）形成在半导体衬底（102）的主表面（104）上。 在栅极结构（112）的侧壁附近形成连续的氮化物间隔物（118,128）。 使用单个蚀刻来蚀刻和凹入氮化物间隔物（118,128）以暴露栅极结构（112）的上部（115A，117A）。 源极（132）和漏极（134）区域形成在半导体衬底（102）中。 在栅极结构（112）和源极区（132）和漏极区（134）的顶表面（109）和暴露的上部（115A，117A）上形成硅化物区域（140,142,144）。 电极（150,152,154）形成为与相应的栅极结构（112），源极区（132）和漏极区（134）的硅化物（140,142,144）接触。