公开(公告)号：US20050250317A1

公开(公告)日：2005-11-10

申请号：US11182150

申请日：2005-07-15

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/44

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

公开(公告)号：US06306691B1

公开(公告)日：2001-10-23

申请号：US09470505

申请日：1999-12-22

申请人： Risho Koh

发明人： Risho Koh

IPC分类号： H01L2100

CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78648

摘要： In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.

摘要翻译： 在体驱动的SOIMOSFET中，半导体层在绝缘体上方延伸，并且包括第一导电型高杂质浓度扩散层，低杂质浓度区和另一第一导电型高杂质浓度扩散层。 形成与低杂质浓度区域的顶部接触的第二导电型高杂质浓度半导体层。 底部电极形成在绝缘层内，使得底部电极被绝缘层包围。 底部电极位于低杂质浓度区域的下方，并由绝缘层与低杂质浓度区域分开。 重要的是，底部电极不会在第一导电性高杂质浓度区域之下延伸。

公开(公告)号：US5668046A

公开(公告)日：1997-09-16

申请号：US413613

申请日：1995-03-30

申请人： Risho Koh ,  Atsushi Ogura

发明人： Risho Koh ,  Atsushi Ogura

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78678 ,  Y10S148/026 ,  Y10S148/053 ,  Y10S148/164

摘要： In a field intensity relaxation of the drain end of a MOSFET, a projective area is not increased with a reduced electrostatic coupling of the source or drain with the gate. The MOSFET satisfying such condition is fabricated on the SOIS film formed by processes of the lateral vapor phase epitaxial growth and the like. A U-shape low concentration impurity region is provided on a gate electrode through a gate dioxide film and high concentration impurity regions are formed at the tops of protrusions. The gate electrode is embedded in insulation films, and the transistor region is fabricated by the lateral vapor phase epitaxial growth and the like.

摘要翻译： 在MOSFET的漏极端的场强弛豫中，投影区域不会随着源极或漏极与栅极的静电耦合减小而增加。 满足这种条件的MOSFET在由侧向气相外延生长等的工艺形成的SOIS膜上制造。 通过栅极二氧化物膜在栅电极上设置U形低浓度杂质区，在突起的顶部形成高浓度杂质区。 栅电极嵌入在绝缘膜中，晶体管区域由横向气相外延生长等制成。

公开(公告)号：US20050151172A1

公开(公告)日：2005-07-14

申请号：US10490599

申请日：2002-10-02

申请人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

发明人： Hisashi Takemura ,  Risho Koh ,  Yukishige Saito ,  Jyonu Ri

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/78696 ,  H01L21/26586 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  H01L2029/7863

摘要： A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.

摘要翻译： 半导体器件包括第一绝缘层，形成在第一绝缘层上的半导体层，半导体层的一部分上的第二绝缘层和通过第二绝缘层形成在半导体层上的栅电极。 半导体层包括通过第二绝缘层形成在栅电极下方的低浓度区域，通过第二绝缘层形成在栅电极下方的低浓度区域的至少上侧区域中的至少上部区域的两个高浓度区域，以及 分别具有高于低浓度区域的杂质浓度的杂质浓度，以及分别形成在高浓度区域的侧部的两个源极/漏极区域，以分别具有低浓度区域侧端部。 高浓度区域的宽度等于或小于30nm。

公开(公告)号：US20120187975A1

公开(公告)日：2012-07-26

申请号：US13351851

申请日：2012-01-17

申请人： Risho Koh ,  Takahiro Iizuka

发明人： Risho Koh ,  Takahiro Iizuka

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： A semiconductor device evaluation apparatus includes a current measurement portion that measures a current value at multiple times included in a period from the beginning of application of a voltage to a semiconductor device to a steady state of the current value flowing through the semiconductor device; a period division portion that divides the period into a first period and a second period later than the first period and finds a curve approximately representing a temporal change in a current value measured at time included in the second period so that a difference between a current value measured at the time included in the first period and a current value found by extrapolating the curve at the same time becomes greater than a specified threshold value; and a current estimation portion that estimates a current value flowing through the semiconductor device at the start time.

摘要翻译： 半导体器件评估装置包括电流测量部分，其测量从开始施加电压到半导体器件的时间段到流过半导体器件的电流值的稳定状态的多个时间的电流值; 周期分割部分，其将该周期划分为比第一周期晚的第一周期和第二周期，并且找到近似表示在包括在第二周期中的时间测量的当前值的时间变化的曲线，使得当前值 在第一期间所包含的时间内进行测定，同时通过外推曲线求出的当前值变得大于规定的阈值; 以及当前估计部分，其估计在开始时流过半导体器件的电流值。

公开(公告)号：US6049110A

公开(公告)日：2000-04-11

申请号：US883442

申请日：1997-06-26

申请人： Risho Koh

发明人： Risho Koh

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/337 ,  H01L29/786 ,  H01L29/808 ,  H01L21/265

CPC分类号： H01L29/66772 ,  H01L29/78648 ,  H01L29/785

摘要： In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.

摘要翻译： 在体驱动的SOIMOSFET中，半导体层在绝缘体上方延伸，并且包括第一导电型高杂质浓度扩散层，低杂质浓度区和另一第一导电型高杂质浓度扩散层。 形成与低杂质浓度区域的顶部接触的第二导电型高杂质浓度半导体层。 底部电极形成在绝缘层内，使得底部电极被绝缘层包围。 底部电极位于低杂质浓度区域的下方，并由绝缘层与低杂质浓度区域分开。 重要的是，底部电极不会在第一导电性高杂质浓度区域之下延伸。

公开(公告)号：US5770506A

公开(公告)日：1998-06-23

申请号：US881749

申请日：1997-06-24

申请人： Risho Koh

发明人： Risho Koh

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L21/28105 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： On a silicon substrate in which boron (B) has been introduced, an n.sup.+ polysilicon film and a tungsten silicide film are sequentially deposited, with a gate oxide film being interposed between the substrate and the polysilicon film, to form a gate electrode. A sidewall of p.sup.+ polysilicon is formed at each side of said gate electrode. A source/drain diffusion layer of an n.sup.+ region is self-aligned with a side edge portion of the gate electrode including the sidewall. The formation of the sidewall is performed after the source/drain diffusion layers have been formed using a dummy sidewall. The gate structure thus formed has a steep potential gradient in the lateral direction of channel region. In the field effect transistor thus formed, the short channel effect is efficiently suppressed.

摘要翻译： 在其中已经引入硼（B）的硅衬底上，依次沉积n +多晶硅膜和硅化钨膜，栅极氧化膜插入在衬底和多晶硅膜之间，以形成栅电极。 在所述栅电极的每一侧形成p +多晶硅的侧壁。 n +区域的源极/漏极扩散层与包括侧壁的栅电极的侧边缘部分自对准。 在使用虚拟侧壁形成源极/漏极扩散层之后进行侧壁的形成。 如此形成的栅极结构在沟道区域的横向上具有陡峭的电位梯度。 在如此形成的场效应晶体管中，有效地抑制了短沟道效应。

公开(公告)号：US5545586A

公开(公告)日：1996-08-13

申请号：US242147

申请日：1994-05-13

申请人： Risho Koh

发明人： Risho Koh

IPC分类号： H01L21/205 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L21/20

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/7834

摘要： On the substrate of an integrated circuit chip is deposited a first insulating layer in which a low resistivity semiconductor region is subsequently formed. An insulating film is formed on a side wall of the low resistivity semiconductor region. A slit is formed in the first insulating layer so that a portion of the substrate and a portion of the insulating film are exposed. First, second and third semiconductor layers of different conductivity types are epitaxially grown in the slit so that the second layer is in contact with the exposed insulating film. A second insulating layer is deposited on the chip. Through the second insulating layer first, second and third electrodes are brought into contact with the first and third semiconductor layers and with the low resistivity semiconductor region. Due to the stacking of epitaxial layers of different conductivity types, the impurity profiles of the epitaxial layers can be precisely controlled.

摘要翻译： 在集成电路芯片的衬底上沉积第一绝缘层，其中随后形成低电阻率半导体区域。 绝缘膜形成在低电阻率半导体区域的侧壁上。 在第一绝缘层中形成狭缝，使得基板的一部分和绝缘膜的一部分露出。 首先，不同导电类型的第二和第三半导体层在狭缝中外延生长，使得第二层与暴露的绝缘膜接触。 第二绝缘层沉积在芯片上。 通过第一绝缘层，第二和第三电极与第一和第三半导体层和低电阻率半导体区域接触。 由于不同导电类型的外延层的堆叠，可以精确地控制外延层的杂质分布。

公开(公告)号：US08633726B2

公开(公告)日：2014-01-21

申请号：US13351851

申请日：2012-01-17

申请人： Risho Koh ,  Takahiro Iizuka

发明人： Risho Koh ,  Takahiro Iizuka

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： A semiconductor device evaluation apparatus includes a current measurement portion that measures a current value at multiple times included in a period from the beginning of application of a voltage to a semiconductor device to a steady state of the current value flowing through the semiconductor device; a period division portion that divides the period into a first period and a second period later than the first period and finds a curve approximately representing a temporal change in a current value measured at time included in the second period so that a difference between a current value measured at the time included in the first period and a current value found by extrapolating the curve at the same time becomes greater than a specified threshold value; and a current estimation portion that estimates a current value flowing through the semiconductor device at the start time.

摘要翻译： 半导体器件评估装置包括电流测量部分，其测量从开始施加电压到半导体器件的时间段到流过半导体器件的电流值的稳定状态的多个时间的电流值; 周期分割部分，其将该周期划分为比第一周期晚的第一周期和第二周期，并且找到近似表示在包括在第二周期中的时间测量的当前值的时间变化的曲线，使得当前值 在第一期间所包含的时间内进行测定，同时通过外推曲线求出的当前值变得大于规定的阈值; 以及当前估计部分，其估计在开始时流过半导体器件的电流值。

公开(公告)号：US07611934B2

公开(公告)日：2009-11-03

申请号：US11182150

申请日：2005-07-15

申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.